Cryptographic Co-processor DMA Data Transfer Latency
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Solution Overview
Problem
Current processing systems face challenges in encrypting and transmitting data efficiently, particularly in automotive applications, where significant data volumes and latency issues arise due to the need for processing core involvement in encryption processes.
Innovation Solution
A processing system incorporating a cryptographic co-processor, such as an AES co-processor, and a Serial Inter-Processor Interface (SIPI) communication interface, which utilizes DMA channels to manage data transfer and encryption operations independently of the processing core, enabling efficient encryption and transmission of data without significant processing core involvement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processing core is involved in encryption operations, then the processing system can perform encryption functions, but latency increases and bandwidth utilization deteriorates
Solution Approach 1:
The patent extracts the encryption function from the processing core by introducing a dedicated cryptographic co-processor. This co-processor handles all encryption operations independently, allowing the processing core to focus on data processing while the cryptographic co-processor manages security operations without blocking or delaying the main processing flow.
Solution Approach 2:
The patent segments the processing system into distinct functional units: a processing core for data processing and a separate cryptographic co-processor for encryption operations. This segmentation allows both functions to operate simultaneously and independently, improving overall productivity while reducing latency through parallel processing.
2Device complexity
If the processing core manages data transfer and encryption, then the system structure remains simple, but device complexity increases when adding cryptographic co-processor and DMA channels
Solution Approach 1:
The patent introduces DMA channels as intermediary components that mediate between the processing core, cryptographic co-processor, and memory. These DMA channels automatically manage data transfer operations without requiring continuous intervention from the processing core, simplifying the interaction between components while enabling efficient parallel data transmission.
Solution Approach 2:
The cryptographic co-processor is designed with multi-functionality, handling both encryption operations and data transfer coordination through integrated DMA interfaces. This universal design reduces the need for separate dedicated hardware components, maintaining architectural simplicity while improving data transmission efficiency.
3Reliability
If encryption operations block data transmission, then processing accuracy is maintained, but bandwidth utilization decreases
Solution Approach 1:
The patent ensures continuity of useful action by enabling the cryptographic co-processor to perform encryption operations independently and concurrently with data transmission activities. The DMA channels maintain continuous data flow between memory and processing units, while the cryptographic co-processor continuously encrypts data without blocking the transmission pipeline, thus maintaining both accuracy and bandwidth utilization.
Data Source
AI summary
In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.