Infield Crypto Engine Testing via LFSR and MISR
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Solution Overview
Problem
Current techniques for testing cryptographic circuitry in multi-die systems, such as those in cloud computing infrastructure, fail to detect defects in crypto engines due to long power cycle intervals and lack of granularity, leading to potential data security breaches and undetected errors.
Innovation Solution
Infield periodic testing using a combination of Linear-Feedback Shift Register (LFSR) and Multiple Input Signature Register (MISR) to generate random patterns that exercise 100% of crypto engine logic, allowing for opportunistic scanning during idle times and spread across multiple test intervals, ensuring comprehensive defect detection and repair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power cycle intervals are extended to maintain system operation, then system availability is improved, but defect detection capability deteriorates
Solution Approach 1:
The patent implements periodic testing during idle times before defects can compromise data security. The LFSR generates test patterns and the MISR captures responses during predetermined idle periods, enabling proactive defect detection without requiring power cycles. This preliminary action ensures crypto engines are tested before potential security breaches occur.
Solution Approach 2:
The patent employs periodic testing at predetermined intervals during idle times to balance system availability with defect detection. Rather than continuous testing that would reduce availability, periodic testing during naturally occurring idle periods maintains both system operation and security monitoring, resolving the contradiction between availability and detection capability.
2Measurement precision
If comprehensive testing patterns are applied to cover 100% of crypto engine logic, then defect detection capability is improved, but testing complexity increases
Solution Approach 1:
The patent introduces LFSR and MISR as intermediary components that simplify comprehensive testing. The LFSR automatically generates deterministic test patterns covering 100% of logic, and the MISR compactly captures and compares responses. These intermediaries eliminate the need for complex manual test sequence design while ensuring complete logic coverage, thus improving detection capability without proportionally increasing testing complexity.
Solution Approach 2:
The patent changes the testing approach from manual/comprehensive step-by-step verification to automated parameter-based testing using LFSR seed values and MISR comparison signatures. By transforming test patterns into deterministic parameter sequences generated by LFSR, the system achieves 100% logic coverage through systematic parameter variation rather than complex procedural testing.
3Measurement precision
If periodic testing is implemented during idle times, then defect detection is improved, but testing frequency is limited by idle time availability
Solution Approach 1:
The patent enables the crypto engine to test itself during its own idle times without requiring external testing resources or system shutdown. The LFSR and MISR are integrated within the crypto engine, allowing it to autonomously generate test patterns and evaluate its own functionality during naturally occurring idle periods. This self-service approach maximizes testing frequency within available idle time windows.
Solution Approach 2:
The patent designs the LFSR and MISR components to serve dual functions: normal operational data processing and cryptographic testing. During idle times, the same hardware resources are repurposed for defect detection, eliminating the need for dedicated testing infrastructure. This multi-functionality enables frequent testing during idle periods without requiring separate testing hardware that would increase overall system complexity.
Data Source
AI summary
Examples include techniques for infield testing of cryptographic circuitry located on a die. The infield testing to include providing a pass or fail status of an infield test scan of the cryptographic circuitry based on comparing an output generated by the cryptographic circuitry during a test run to a signature. The output generated by the cryptographic circuitry is in response to an input generated by a linear-feedback shift register during the test run.