Hardware Cryptographic Engine Memory Buffering
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Solution Overview
Problem
Existing hardware cryptographic engines are complex and occupy a large area on integrated circuits, requiring significant memory and power consumption, which makes them costly and inefficient.
Innovation Solution
A hardware cryptographic engine with a direct-memory-access (DMA) input module and a cryptographic module that includes an input register and alignment circuitry, where input data is buffered in an alignment buffer of less than twice the input-register length, allowing for efficient alignment and processing without extensive buffering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a hardware cryptographic engine uses extensive buffering and complex memory management, then data processing capability is improved, but device complexity and memory usage increase
Solution Approach 1:
The patent extracts the buffering function from the cryptographic engine itself and places it in external memory, accessed via DMA. This removes the need for internal buffers within the cryptographic engine, significantly reducing its complexity while maintaining the ability to process large amounts of data through external memory resources.
Solution Approach 2:
The patent introduces a DMA controller as an intermediary between external memory and the cryptographic engine. This mediator handles all memory access operations, allowing the cryptographic engine to focus solely on cryptographic processing without needing complex memory management logic internally.
2Productivity
If a hardware cryptographic engine includes extensive buffering, then data processing capability is improved, but power consumption increases
Solution Approach 1:
By extracting the buffering function to external memory and implementing it without complex control logic, the patent significantly reduces the active circuitry within the cryptographic engine, thereby reducing power consumption while maintaining data processing capability.
Solution Approach 2:
The DMA controller autonomously manages data transfer between external memory and the cryptographic engine without requiring processor intervention. This self-service approach eliminates the need for power-consuming processor cycles dedicated to memory management, reducing overall system power consumption.
3Device complexity
If a hardware cryptographic engine uses minimal buffering, then device complexity is reduced, but data processing efficiency may worsen
Solution Approach 1:
The patent merges the buffering capacity with external memory resources rather than dedicating separate buffer memory within the cryptographic engine. This consolidation allows the system to utilize existing memory infrastructure, reducing overall device complexity while maintaining adequate buffering capacity for efficient data processing.
Solution Approach 2:
The DMA controller serves as an efficient intermediary that optimizes data flow between external memory and the cryptographic engine, ensuring high data processing efficiency despite minimal internal buffering. The DMA's optimized transfer protocols and batch processing capabilities maintain throughput while minimizing the need for complex internal buffer management.
Data Source
AI summary
A hardware cryptographic engine comprises a direct-memory-access (DMA) input module for receiving input data over a memory bus, and a cryptographic module. The cryptographic module comprises an input register having an input-register length, and circuitry configured to perform a cryptographic operation on data in the input register. The hardware cryptographic engine further comprises an input-alignment buffer having a length that is less than twice said input-register length, and alignment circuitry performing an alignment operation on input data in the input-alignment buffer. The hardware cryptographic engine is configured to pass input data, received by the DMA input module, from the memory bus to the input register of the cryptographic module after buffering an amount of input data no greater than the length of the input-alignment buffer.