Cryptographic Memory Cell Array with Segmented Resistance States
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Solution Overview
Problem
Current cryptographic processing devices lack a secure data storage method in non-volatile memory devices, as existing techniques do not provide adequate protection against unauthorized access and data integrity.
Innovation Solution
A cryptographic processing device with a memory cell array that includes memory cells with variable and initial states, where the resistance value changes reversibly between multiple ranges based on electric signals, allowing for secure data storage by determining the state of each memory cell to store conversion parameter data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional data storage methods are used in non-volatile memory devices, then data can be stored, but data security and protection against unauthorized access are insufficient
Solution Approach 1:
The patent applies parameter changes by utilizing the resistance value of memory cells as a security parameter. Memory cells are configured to have resistance values within specific ranges that correspond to different data states. The system changes the resistance parameter of memory cells to encode conversion parameter data securely, making it difficult to access without proper authorization. This parameter-based storage approach enhances data security while managing memory cell states through controlled resistance transitions.
2Ease of manufacture
If memory cells are made to change state easily for data storage, then data writing is simplified, but data integrity and protection against unauthorized modification are compromised
Solution Approach 1:
The patent applies local quality by differentiating the characteristics of memory cells based on their resistance value ranges. Memory cells are categorized into different groups with distinct resistance ranges, where each range corresponds to a specific data state. This local differentiation allows the system to maintain data integrity by ensuring that only authorized operations can transition memory cells between specific resistance ranges, while still allowing easy data storage within the defined ranges.
3Adaptability or versatility
If overlapping resistance value ranges are used in memory cells, then more data states can be represented, but measurement precision and data accuracy deteriorate
Solution Approach 1:
The patent applies segmentation by dividing the resistance value spectrum into distinct, non-overlapping ranges, each representing a specific data state. Instead of allowing continuous or overlapping resistance values, the system segments the resistance range into discrete intervals with clear boundaries. This segmentation ensures that each memory cell's resistance value unambiguously corresponds to one data state, maintaining high measurement precision while still representing multiple data states through the segmented ranges.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a safer encryption technique by securely storing data based on the state of memory cells, enhancing data protection and integrity in non-volatile memory devices.
Implementation Method 1
a memory cell in a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied thereto
Implementation Method 2
a memory cell in an initial state, which does not change to the variable state unless a forming stress for changing the memory cell in the initial state to the variable state is applied thereto
Data Source
AI summary
A cryptographic processing device comprises a cipher control circuit operative to execute at least one of encryption of plaintext data and decryption of ciphertext data on the basis of conversion parameter data; and a memory cell array that includes a plurality of memory cells, the plurality of memory cells including: a memory cell in a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied thereto; and a memory cell in an initial state, which does not change to the variable state unless a forming stress for changing the memory cell in the initial state to the variable state is applied thereto, a resistance value of the memory cell in the initial state being within an initial resistance value range which does not overlap with the plurality of changeable resistance value ranges, wherein in the memory cell array, data including the conversion parameter data is stored on the basis of whether each of the plurality of memory cells is in the initial state or the variable state.