Crypto Processor Parallel Polynomial Multiplication
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Solution Overview
Problem
Current homomorphic encryption methods face inefficiencies in polynomial multiplication operations, particularly in lattice-based systems, due to increased noise levels and computational overhead, which can overwhelm data processing and compromise privacy.
Innovation Solution
A crypto processor is designed to perform polynomial multiplication of lattice-based texts by transferring coefficients for parallel multiplication and addition operations, utilizing multipliers and an adder to efficiently process coefficients, and determining results through internal data paths, with optional mode control for different operation scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If polynomial multiplication is performed using conventional sequential methods, then computational accuracy is maintained, but processing speed and efficiency deteriorate
Solution Approach 1:
The polynomial multiplication process is segmented into multiple parallel operations: coefficient extraction, NTT transformation, point-wise multiplication, and inverse NTT. The processor is divided into specialized units (multipliers, adders, transformers) that handle specific segments of the computation simultaneously, achieving parallel processing of polynomial coefficients while maintaining computational accuracy
Solution Approach 2:
The patent transforms the one-dimensional sequential polynomial multiplication into a multi-dimensional parallel computation space by applying Number Theoretic Transform (NTT). This converts polynomial multiplication into point-wise multiplication in the frequency domain, enabling simultaneous computation of multiple coefficient products across different dimensions (frequencies), thereby dramatically improving processing speed
2Reliability
If noise levels are reduced to maintain data privacy, then security is improved, but computational overhead increases
Solution Approach 1:
The patent optimizes noise management by dynamically adjusting cryptographic parameters (security levels, polynomial degrees, modulus values) based on the specific computation requirements. This allows the system to use minimal necessary noise for each operation, reducing computational overhead while maintaining adequate security margins for data privacy
Solution Approach 2:
Noise management operations (noise addition, noise scaling, noise reduction) are performed preliminarily before polynomial multiplication and embedded within the computation pipeline. By preparing noise parameters in advance and integrating noise operations with the main computation flow rather than handling them separately, the system reduces overall computational overhead while ensuring noise levels remain within security bounds
3Productivity
If parallel multiplication operations are increased to improve processing speed, then productivity is improved, but device complexity increases
Solution Approach 1:
The processor employs universal computational units (multipliers and adders) that can handle multiple functions: point-wise multiplication of transformed coefficients, accumulation of partial products, and support for both NTT and inverse NTT operations. This multi-functionality allows parallel processing of multiple polynomial coefficient pairs using the same hardware resources, increasing throughput without proportionally increasing device complexity
Solution Approach 2:
The patent implements a nested computational structure where multiple levels of parallelism are organized hierarchically: individual coefficient multiplications are nested within polynomial transformations, which are nested within the overall encryption/decryption pipeline. This nested organization allows efficient resource sharing and reduces the total number of required computational units compared to fully parallel implementation
Data Source
AI summary
A crypto processor, a method of operating a crypto processor, and an electronic device including a crypto processor. A method of operating a crypto processor for performing a polynomial multiplication of lattice-based texts includes transferring coefficients of polynomials for the polynomial multiplication to multipliers, performing multiplications for a portion of the coefficients in parallel using the multipliers, performing an addition for a portion of results of the multiplications using an adder, and determining a result of the polynomial multiplication based on another portion of the results of the multiplications and a result of the addition.