Cryptoalgorithm Execution via CPU and Hardware Circuit Split
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Solution Overview
Problem
Existing cryptographic algorithms, such as DES and AES, require complex hardware implementations that are costly in terms of chip area and time to market, especially for multi-functional cryptography processors, due to the need for custom design and separate flow control mechanisms for each algorithm, which limits scalability and increases design complexity.
Innovation Solution
A cryptoalgorithm implementation that divides operations into two sub-groups, with a central processing unit handling arithmetic and logic operations and a hardware circuit performing rotation, permutation, and substitution operations, connected via a data bus, allowing for a more economical and faster execution by reducing hardware complexity and leveraging existing CPU components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a custom hardware design is used for each cryptographic algorithm, then the algorithm execution speed is improved, but the chip area and design complexity increase significantly
Solution Approach 1:
The patent implements a universal cryptographic processing platform that can execute multiple cryptographic algorithms (DES, AES, and others) through a single hardware architecture. The CPU executes algorithm-specific instructions while shared hardware circuits perform common operations like rotation, permutation, and substitution, eliminating the need for separate custom designs for each algorithm while maintaining high execution speed.
Solution Approach 2:
The cryptographic processing functionality is segmented into distinct components: a CPU for executing control logic and algorithm-specific operations, and separate hardware circuits for specific cryptographic operations (rotation unit, permutation unit, substitution unit). This segmentation allows the system to maintain speed through dedicated hardware while reducing overall design complexity through modularity and reusability.
2Productivity
If separate flow control mechanisms are implemented for each algorithm, then the algorithm execution is improved, but the design complexity and time to market increase
Solution Approach 1:
A single CPU serves as a universal flow control mechanism for all cryptographic algorithms. The CPU executes algorithm-specific instruction sequences that control the shared hardware circuits, providing the necessary flow control for DES, AES, and other algorithms without requiring separate dedicated control units for each algorithm, thereby reducing design complexity while maintaining full algorithm processing capability.
3Productivity
If custom hardware circuits are designed for each cryptographic algorithm, then the execution efficiency is improved, but the chip area requirements increase
Solution Approach 1:
Shared hardware circuits for rotation, permutation, and substitution operations serve multiple cryptographic algorithms simultaneously. These circuits are controlled by algorithm-specific instructions from the CPU, allowing the same physical hardware to perform different cryptographic functions, thereby maintaining high processing efficiency while significantly reducing the total chip area required compared to having dedicated circuits for each algorithm.
Solution Approach 2:
The patent merges the functionality of multiple algorithm-specific hardware circuits into a single set of shared circuits. The rotation unit, permutation unit, and substitution unit are common resources that are dynamically allocated to different algorithms through CPU control, combining what would traditionally be separate hardware blocks into a unified, area-efficient structure.
4Device complexity
If a purely software implementation is used, then the design complexity is reduced, but the execution speed decreases
Solution Approach 1:
The CPU acts as an intermediary between the software algorithm implementation and the hardware execution units. The CPU executes software instructions that control the shared hardware circuits for rotation, permutation, and substitution operations, combining the simplicity of software implementation with the speed of hardware execution. This hybrid approach avoids the need for purely software execution while maintaining design flexibility.
Data Source
AI summary
A device for executing a cryptoalgorithm including a central processing unit for a first sub-group of operations and for a flow control of the cryptoalgorithm as well as a hardware circuit for a second sub-group of operations, wherein the first sub-group preferably includes arithmetic and/or logic operations, while the second sub-group includes rotation operations, permutation operations, substitution operations or selection operations.