Cryptographic Cache Lines for Trusted Execution Environments
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Solution Overview
Problem
Conventional computer security systems provide low assurance protection for entire computing systems, leaving them vulnerable to hardware and software attacks, particularly in interconnected electronic devices that process and store sensitive information.
Innovation Solution
Implementing a memory encryption engine (MEE) that secures main memory by providing confidentiality and integrity through counter-mode encryption and replay protection, using unique encryption seeds for each cache line and cryptographic cache block, and associating message authentication codes with secure data to prevent unauthorized access and modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional security systems are used to protect the entire computing system, then the system provides basic protection coverage, but the security assurance level remains low and the system is vulnerable to hardware and software attacks
Solution Approach 1:
The patent divides the computing system into distinct security zones: a trusted execution environment (TEE) for high-assurance operations and a non-TEE for standard operations. The TEE is further segmented into isolated regions with separate address spaces, preventing attacks from propagating across the entire system. This segmentation allows critical security functions to be isolated and protected with higher assurance levels.
Solution Approach 2:
The patent introduces a secure monitor as an intermediary component that mediates between the TEE and the rest of the system. This monitor provides attestation services, verifying the integrity of code and data in the TEE, and controls access between trusted and untrusted regions. The intermediary enables high-assurance operations without requiring the entire system to operate at the same security level.
2Reliability
If memory encryption is implemented to protect confidentiality, then data security is improved, but the processing overhead and system complexity increase
Solution Approach 1:
The patent implements self-service memory encryption where the memory encryption engine automatically encrypts and decrypts data in the TEE without requiring explicit software intervention. The encryption keys are managed autonomously by the hardware, and the encryption/decryption operations occur transparently during memory access. This eliminates the need for complex software encryption routines while maintaining strong confidentiality protection.
3Reliability
If integrity protection mechanisms are added to prevent modifications, then security is improved, but the processing time and operational overhead increase
Solution Approach 1:
The patent computes and stores integrity measurement values (such as hash values or message authentication codes) in advance when code or data is loaded into the TEE. These pre-computed integrity values are stored in protected memory alongside the encrypted data. When integrity verification is needed, the system simply compares the current state against these pre-stored values, avoiding the need to re-compute complex integrity checks during operation.
4Reliability
If replay protection is implemented to eliminate temporal substitution, then security is improved, but the complexity of the protection mechanism increases
Solution Approach 1:
The patent uses replay protection counters stored in protected memory to prevent temporal substitution attacks. Each protected region has an associated counter that is incremented with each access or operation. The system verifies that counter values are monotonically increasing, detecting any replay attempts where old data is reused. This simple parameter-based approach provides strong replay protection without requiring complex cryptographic protocols.
Data Source
AI summary
Memory security technologies are described. An example processing system includes a processor core and a memory controller coupled to the processor core and a memory. The processor core can receive a content read instruction from an application. The processor core can identify a cache line (CL) from a plurality of CLs of a cryptographic cache block (CCB) requested in the content read instruction. The processor core can load, from a cryptographic tree, tree nodes with security metadata. The processor core can retrieve, from the memory, the CCB. The processor core can generate a second MAC from the CCB. The processor core can compare the first MAC with the second MAC. The processor core can decrypt the CCB using security metadata when the first MAC matches the second MAC. The processor core can send at least the identified CL from the decrypted CCB to the application.