Cryptographic Memory Isolation Without Area-Intensive MPUs
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Solution Overview
Problem
Existing memory protection units (MPUs) for small embedded devices are area-intensive and prone to misconfiguration and fault attacks, failing to provide adequate memory isolation security.
Innovation Solution
Implementing a short message authentication code (MAC) in combination with memory encryption and read access validations to enhance memory isolation security, using a symmetric tweakable encryption algorithm and parity bits for error detection, and requiring multiple read accesses for write validation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory protection unit (MPU) is used for memory isolation, then memory security is improved, but device area increases
Solution Approach 1:
The patent extracts the essential security function (memory isolation) from the bulky MPU architecture and implements it using only cryptographic primitives (encryption and MAC) that can be implemented with minimal hardware overhead. The security functionality is separated from the general-purpose processor, allowing the processor to operate normally while cryptographic operations provide the necessary protection.
Solution Approach 2:
The patent uses cryptographic copies (encrypted versions) of the data and authentication tags (MACs) to protect memory contents. Instead of physically isolating memory regions with complex hardware boundaries, the system creates cryptographic replicas that provide the same security function with minimal area overhead.
2Reliability
If logical isolation (firewall) is used for memory protection, then memory security is improved, but the system becomes prone to misconfiguration and fault attacks
Solution Approach 1:
The patent replaces the mechanical/configuration-based firewall system with a cryptographic system. Instead of relying on software firewalls that require manual configuration and are prone to human error, the system uses mathematical cryptographic functions (encryption and MAC verification) that provide automatic, configuration-free security. The security properties emerge from the cryptographic algorithms themselves rather than from configured rules.
3Reliability
If multiple read access validations are required before write access, then memory security is improved, but access time increases
Solution Approach 1:
The patent performs read validations as preliminary actions before allowing write operations. By requiring multiple successful read validations (checking MACs) before permitting a write, the system ensures that the memory region is accessible and the authentication mechanism works correctly. This preliminary verification prevents undetected writes while the cryptographic operations occur in parallel with normal processing where possible.
Data Source
AI summary
A data processing system is provided that includes a memory, a processor, and a memory integrity circuit. The memory includes a plurality of memory regions configured to store information. The processor is configured to execute instructions to access an address in the memory. The memory integrity circuit is coupled to the processor and to the memory, and configured to validate read and write accesses to the memory by the processor. The memory integrity circuit validates a write access to an address of a memory region of the plurality of memory regions in response to n number of the read accesses being validated prior to the write access, where n is an integer, and in response to correctly calculating a message authentication code (MAC) of a combination of encrypted data stored at the address and a tweak value. In another embodiment, a method is provided for isolation security for the memory.