Cryptographic NTT Accelerator With Pipelined Butterfly Circuits
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Solution Overview
Problem
Quantum computers pose a threat to the security of existing public-key cryptosystems, and existing designs for accelerating Number Theoretic Transform (NTT) computations, such as pipelined and parallel architectures, incur high circuitry area or memory access overhead.
Innovation Solution
A cryptographic accelerator combines pipelined and parallel butterfly operator circuits to perform NTT/INTT operations, utilizing registers to reduce memory access overhead and efficiently process polynomial coefficients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pipelined architectures are used to accelerate NTT computations, then computational throughput is improved, but circuitry area increases due to data dependencies between NTT stages
Solution Approach 1:
The NTT computation is divided into multiple stages, with each stage processing a subset of coefficients. This segmentation allows the use of smaller, more manageable butterfly operator circuits at each stage while maintaining overall computational throughput through pipelined execution across stages.
Solution Approach 2:
The patent introduces a temporal dimension to the computation by implementing pipelined execution, where different stages of the NTT computation proceed simultaneously at different clock cycles. This allows throughput improvement without proportionally increasing the spatial circuitry area, as resources are reused across time.
2Speed
If parallel architectures are used to accelerate NTT computations, then computational speed is improved, but memory access overhead increases for providing polynomial coefficients
Solution Approach 1:
Coefficients are pre-loaded into on-chip buffers before the NTT computation begins. This preliminary action ensures that when the parallel butterfly operator circuits need coefficients during computation, they can access them quickly from local memory rather than waiting for slower external memory access, thereby reducing memory access overhead while maintaining high computational speed.
Solution Approach 2:
On-chip buffers serve as intermediary storage between the parallel butterfly operator circuits and external memory. These buffers hold coefficient data locally, allowing fast access for multiple parallel circuits without requiring simultaneous access to external memory, thus reducing memory access overhead while maintaining computational speed.
Data Source
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AI summary
A cryptographic accelerator utilizes a combination of parallel and pipelined butterfly operator circuit to perform number theoretic transform (NTT) or inverse NTT (INTT.) The accelerator includes a first set of pipelined pairs of parallel butterfly operator circuits configured to operate on pairs of polynomial coefficients to provide output coefficients. A first buffer is coupled to store the output coefficients. A second set of pipelined pairs of parallel butterfly operator circuits are configured to operation on pairs of coefficients obtained from the first buffer to provide coefficients of the polynomial in a number theoretic transform (NTT) domain or out of the NTT domain.