Cryptographic Permutation Unit for Low-Resource Secure Processing

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Solution Overview

Problem

Existing cryptographic systems face challenges in providing efficient implementations for low-resource embedded systems and high-speed data processing while ensuring resistance to attacks, especially in a post-quantum computing environment, due to resource-intensive complex mathematical functions and vulnerabilities in cryptographic protocols.

Innovation Solution

A cryptographic architecture that offloads cryptographic permutation computations to a dedicated module, utilizing a processor interface to efficiently perform cryptographic operations, including post-quantum secure functions, through a cryptographic permutation unit, which can be implemented using ASICs, FPGAs, or firmware, and is compatible with various computing devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If complex mathematical functions with long bit lengths are used for post-quantum secure cryptography, then security strength is improved, but processor cycle consumption increases

Engineering Contradiction:
Improvesecurity strengthVSAvoidprocessor cycle consumption
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The cryptographic function is divided into multiple rounds, where each round performs a subset of the total bitwise operations. This segmentation allows the complex post-quantum cryptographic function to be broken down into manageable stages that can be executed efficiently on resource-constrained devices while maintaining the overall security strength through cumulative effect across all rounds.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If cryptographic functions are implemented in software on general-purpose processors, then flexibility and adaptability are improved, but execution speed and resource efficiency deteriorate

Engineering Contradiction:
Improveimplementation flexibilityVSAvoidexecution speed
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

A dedicated cryptographic co-processor or hardware module is introduced as an intermediary between the general-purpose processor and the cryptographic computation. This intermediary handles the resource-intensive cryptographic operations in hardware, allowing the main processor to maintain flexibility while achieving high-speed execution through specialized hardware acceleration.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If cryptographic operations are performed repeatedly at high speeds for end-to-end encryption, then data protection coverage is improved, but resource consumption increases

Engineering Contradiction:
Improvedata protection coverageVSAvoidenergy consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

Cryptographic keys and cryptographic contexts are pre-computed and cached before actual data encryption operations. This preliminary action reduces the computational burden during repeated encryption/decryption operations, allowing high-speed data protection with reduced energy consumption since the most resource-intensive setup operations are performed once rather than repeatedly.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12474891B2Cryptographic architecture for cryptographic permutation
Publication Date: 2025.11.18 PQSHIELD LTD
  • US12474891B2 patent drawing
  • US12474891B2 patent drawing
  • US12474891B2 patent drawing

AI summary

Cryptographic methods and systems are described. Certain examples relate to performing cryptographic operations that involve a cryptographic permutation. The methods and systems may be used to provide cryptographic functions such as hashing, encryption, decryption and random number generation. In one example, a cryptographic architecture is provided. The cryptographic architecture has a processor interface comprising a set of cryptographic registers, where the processor interface is accessible by at least one processing unit. The cryptographic architecture also has a cryptographic permutation unit comprising circuitry to perform a cryptographic permutation using data stored within the set of cryptographic registers. In examples, the at least one processing unit instructs the cryptographic permutation and accesses a result of the cryptographic permutation using the processor interface.