Cryptography Processor With Function Circuits For Post-Quantum Security
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Solution Overview
Problem
Post-quantum cryptography (PQC) algorithms, including lattice-based cryptography, require more storage and computation than conventional algorithms, leading to significant memory and performance overhead in existing systems, necessitating the development of efficient cryptography processors that can operate on both high-performance and low-performance devices.
Innovation Solution
A cryptography processor is designed with a configuration that includes interface circuits for communication with host devices and semiconductor memory, registers for storing intermediate and control data, and a combination of common operation circuits and function circuits. The function circuits control the common operation circuits to perform specific workloads allocated from the host device, allowing for efficient execution of cryptographic operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If post-quantum cryptography algorithms are implemented, then cryptographic security is improved, but storage space and computation requirements increase
Solution Approach 1:
The cryptographic processor divides the cryptographic operation into multiple functions, each handled by dedicated function circuits. These function circuits control shared common operation circuits to perform specific tasks such as polynomial multiplication, vector operations, and modular arithmetic, thereby reducing overall storage requirements while maintaining security
Solution Approach 2:
The patent implements common operation circuits that can be controlled by different function circuits to execute multiple cryptographic functions. This multi-functional approach allows the same hardware resources to be reused across different PQC operations, significantly reducing the storage space and computational overhead compared to implementing separate dedicated circuits for each function
2Reliability
If post-quantum cryptography algorithms are implemented, then cryptographic security is improved, but computation requirements increase
Solution Approach 1:
The cryptographic processor segments PQC operations into distinct function circuits (e.g., polynomial multiplication, vector operations, modular arithmetic) that can be executed efficiently. Each function circuit is optimized for its specific task, reducing the overall computational complexity compared to general-purpose implementations
Solution Approach 2:
Common operation circuits are designed to be controllable by multiple function circuits, enabling them to perform various cryptographic operations. This universality reduces computation requirements by avoiding redundant circuit implementations and enabling efficient resource utilization across different PQC algorithms
3Productivity
If dedicated cryptography processors are designed, then performance is improved, but device area increases
Solution Approach 1:
The cryptographic processor uses common operation circuits that can be controlled by different function circuits to execute multiple cryptographic functions. This shared resource approach significantly reduces the device area compared to implementing separate dedicated circuits for each function, while still achieving high performance through optimized control and execution
Solution Approach 2:
The patent implements dynamic control mechanisms where function circuits can selectively activate and control common operation circuits based on the specific cryptographic operation required. This dynamic resource allocation optimizes performance for each operation while minimizing the active device area, allowing the processor to adapt to different computational needs without permanently allocating resources for all possible functions
Data Source
AI summary
A cryptography processor includes at least one interface circuit configured to communication with at least one of a host device and a semiconductor memory device, at least one register configured to store at least one of intermediate data of a common operation and control data received from the host device, a plurality of common operation circuits, respectively configured to perform different operations, and a plurality of function circuits configured to control at least one of the plurality of common operation circuits to perform a workload allocated from the host device. At least one of the plurality of common operation circuits may be configured to be controlled by different function circuits, among the plurality of function circuits, to execute different functions of a cryptographic operation, and the workload may be configured to execute a function of the cryptographic operation.