Crystal-Less Clock Generator With Feedback Frequency Calibration

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Solution Overview

Problem

Existing CMOS oscillators are sensitive to environmental variations such as temperature and voltage changes, which affects the stability of the clock signal frequency, making it challenging to maintain frequency stability in electronic systems.

Innovation Solution

A crystal-less clock generator (CLCG) comprising a first oscillation circuit, a second oscillation circuit, and a control circuit that automatically calibrates the output frequency by generating a control signal based on the relationship between the output clock signal and a reference clock signal, allowing for compensation of frequency errors caused by environmental variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a crystal oscillator or MEMS is used to generate clock signal, then frequency stability is improved, but device area and power consumption increase

Engineering Contradiction:
Improvefrequency stabilityVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts the frequency stabilization function from the physical crystal oscillator and implements it through a digital control circuit that measures and adjusts the CMOS oscillator frequency based on temperature, thereby eliminating the need for large crystal components while maintaining stability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the mechanical crystal oscillator system with an all-digital CMOS system that uses temperature sensing and digital frequency adjustment to achieve the same frequency stabilization function, thereby reducing device area and power consumption

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If a crystal oscillator or MEMS is used to generate clock signal, then frequency stability is improved, but power consumption increases

Engineering Contradiction:
Improvefrequency stabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent extracts the frequency stabilization function from the power-hungry crystal oscillator and implements it through a low-power digital control circuit that measures temperature and adjusts the CMOS oscillator frequency accordingly

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent substitutes the high-power crystal oscillator with an all-digital CMOS system that achieves frequency stability through temperature-compensated digital control, significantly reducing power consumption

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Ease of manufacture

If CMOS oscillation circuit is used, then integration is improved, but frequency stability deteriorates due to temperature sensitivity

Engineering Contradiction:
ImproveintegrationVSAvoidfrequency stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent introduces a feedback mechanism where the measured frequency or temperature information is fed back to the control circuit, which then adjusts the CMOS oscillator parameters to compensate for temperature drift and maintain frequency stability

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent changes the operating parameters of the CMOS oscillator based on temperature measurements, adjusting frequency control parameters dynamically to compensate for temperature-induced frequency drift and maintain stability

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9024693B2Crystal-less clock generator and operation method thereof
Publication Date: 2015.05.05 IND TECH RES INST
  • US9024693B2 patent drawing
  • US9024693B2 patent drawing
  • US9024693B2 patent drawing

AI summary

A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.