Crystal-Less Jitter Attenuator With Fractional Clock Cleanup
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing jitter attenuators require large die area, high power consumption, and increased production costs due to the use of external crystals and complex off-chip architectures, which are inefficient for low power and small footprint applications.
Innovation Solution
An integrated circuit with a signal comparator, digital low pass filter, and a free running crystal-less oscillator that uses a fractional output divider to produce a clean clock signal, eliminating the need for external crystals and reducing complexity, while incorporating temperature compensation for stable frequency operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external crystal is used in the jitter attenuator, then frequency stability is improved, but device area and power consumption increase
Solution Approach 1:
The patent extracts and eliminates the external crystal component from the jitter attenuator system. Instead of using an off-chip crystal oscillator, the invention implements an on-chip voltage-controlled oscillator (VCO) that generates the reference clock signal directly within the integrated circuit, thereby removing the need for external crystals and reducing die area while maintaining frequency stability through digital control mechanisms
Solution Approach 2:
The patent merges the functions of the external crystal oscillator and the jitter attenuation circuitry into a single integrated chip. The VCO, phase detector, loop filter, and output divider are combined into one unified on-chip system, eliminating separate external components and reducing overall device area while maintaining the jitter attenuation function
2Reliability
If an external crystal is used in the jitter attenuator, then frequency stability is improved, but power consumption increases
Solution Approach 1:
The patent removes the power-hungry external crystal oscillator from the system and replaces it with a more power-efficient on-chip VCO. The VCO consumes significantly less power while achieving comparable frequency stability through digital control and feedback mechanisms integrated within the chip
Solution Approach 2:
The patent changes the operating parameters by using a digitally controlled VCO instead of a fixed-frequency crystal oscillator. This allows dynamic adjustment of the reference frequency through digital control words, enabling the system to maintain frequency stability across different operating conditions while optimizing power consumption for each specific frequency requirement
3Reliability
If an external crystal is used in the jitter attenuator, then frequency stability is improved, but manufacturing cost increases
Solution Approach 1:
The patent extracts and eliminates the external crystal component, which is a separate bill-of-materials item requiring additional packaging and assembly steps. By integrating the oscillator function on-chip, the invention simplifies the manufacturing process, reduces assembly complexity, and eliminates the cost of external crystal components while maintaining frequency stability
Solution Approach 2:
The patent combines multiple functions (jitter attenuation, frequency synthesis, and clock generation) into a single integrated circuit chip. This consolidation reduces the number of discrete components, simplifies assembly processes, and enables higher production volumes with lower per-unit costs while maintaining the required frequency stability for Ethernet and HDMI applications
4Reliability
If a complex off-chip architecture is used, then jitter attenuation performance is improved, but device complexity increases
Solution Approach 1:
The patent merges the jitter attenuation loop components (phase detector, loop filter, VCO control) with the frequency synthesis function into a single integrated on-chip architecture. This unified design reduces the complexity of interconnections and control logic while maintaining effective jitter attenuation performance through coordinated on-chip operation of all loop components
Data Source
AI summary
An integrated circuit to remove jitter from a clock signal includes an integrated circuit die. The integrated circuit die includes a signal comparator. The signal comparator is configured to determine a frequency difference between a jittery input clock signal and a correction signal. A digital low pass filter is coupled to receive and filter the frequency difference and to provide a filtered output signal. A free running crystal-less oscillator produces a reference signal. A fractional output divider is coupled to the free running crystal-less oscillator and the digital low pass filter. The fractional output divider utilizes the filtered output signal to establish a value to divide the reference signal by to obtain a clean output clock signal. The clean output clock signal is fed back to the signal comparator and is used as the correction signal.