Crystal Oscillation Device Parasitic Capacitance Reduction
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Solution Overview
Problem
Crystal oscillation devices face challenges in reducing power consumption while maintaining low load capacitance values, leading to issues with parasitic capacitance, noise tolerance, and adaptability to varying power source voltages when using low CL value quartz crystal units.
Innovation Solution
A crystal oscillation device configuration with a semiconductor package and quartz crystal unit on a printed circuit board, featuring specific wiring patterns and capacitor connections to reduce parasitic capacitance and noise, and a semiconductor device with a reference current generating circuit and comparator circuit to manage current and voltage for low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a low CL value quartz crystal unit is used to reduce power consumption, then power consumption is reduced, but parasitic capacitance and noise tolerance deteriorate
Solution Approach 1:
A ground wiring pattern is introduced as an intermediary element between the signal wiring patterns connected to the quartz crystal unit. This ground wiring acts as a shield that isolates the low-capacitance signal paths from parasitic capacitance and noise, enabling the use of low CL value crystal units while maintaining signal integrity and noise tolerance.
Solution Approach 2:
The patent applies different wiring configurations to different regions: ground wiring patterns are specifically placed near the quartz crystal unit connections where parasitic capacitance is most problematic, while other areas use standard wiring. This localized approach reduces parasitic effects at critical points without unnecessarily complicating the entire circuit.
2Stability of the object's composition
If the semiconductor device is disposed near power source terminals to minimize voltage drop, then voltage stability is improved, but adaptability to varying power source voltages deteriorates
Solution Approach 1:
The patent implements a voltage detection circuit that dynamically monitors the power source voltage and adjusts the reference voltage accordingly. This dynamic adjustment mechanism allows the device to adapt to varying power source voltages (e.g., 1.7V to 5.5V) while maintaining stable operation, resolving the contradiction between voltage stability and voltage adaptability.
Solution Approach 2:
A feedback mechanism is introduced where the detected power source voltage is used to adjust the reference voltage in the comparison circuit. This feedback loop ensures that the device maintains proper operation across different power source voltages by continuously adapting the reference level to match the actual power source conditions.
Data Source
AI summary
A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.