Crystal Oscillator Back-Gate Biasing for Fast Stable Startup
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Solution Overview
Problem
Crystal oscillators face challenges in achieving fast startup times and stable oscillation due to variations in crystal properties, amplifier process variations, and temperature fluctuations, particularly in advanced processing technologies like low-power deep submicron CMOS, where negative resistance is difficult to achieve.
Innovation Solution
A crystal oscillator design that includes a back gate bias control circuit to adjust the body bias of NMOS and PMOS transistors in the inverter, enhancing negative resistance during startup and steady-state operation, using body resistors, controllable current sources, and reference voltage control to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a crystal oscillator is designed for fast startup time, then the negative resistance must be sufficiently high to overcome crystal losses quickly, but this requires advanced processing technologies and precise control to maintain stability
Solution Approach 1:
The patent applies dynamics by making the body bias voltage adjustable and time-dependent. The bias voltage is dynamically changed from a first level during startup to a second level during steady-state operation, allowing the oscillator to optimize negative resistance during startup and then maintain stability during normal operation. This dynamic adjustment resolves the contradiction between fast startup and stable oscillation.
Solution Approach 2:
The patent changes the body bias voltage parameter of the transistors to control negative resistance. By adjusting the body bias voltage level, the negative resistance of the inverter is optimized during startup to achieve fast oscillation establishment, and then adjusted to maintain stable oscillation during steady-state operation. This parameter change approach directly addresses the startup time versus stability contradiction.
2Use of energy by moving object
If advanced processing technologies like low-power deep submicron CMOS are used, then power consumption is reduced, but achieving sufficient negative resistance becomes difficult
Solution Approach 1:
The patent compensates for the reduced negative resistance in advanced CMOS technologies by adjusting the body bias voltage parameter. By applying optimized body bias voltages to the NMOS and PMOS transistors, the negative resistance is enhanced to sufficient levels while maintaining the low-power benefits of advanced processing technologies. This allows the oscillator to achieve both low power consumption and reliable oscillation.
Solution Approach 2:
The body bias control circuit acts as an intermediary that mediates between the low-power CMOS technology and the required negative resistance. The control circuit adjusts the body bias voltages to optimize transistor performance and generate sufficient negative resistance, bridging the gap between the capabilities of advanced CMOS and the requirements of reliable oscillation.
3Loss of time
If body bias control circuit is added to adjust negative resistance, then startup time is reduced and phase noise performance is improved, but device complexity increases
Solution Approach 1:
The patent uses a dynamic body bias control approach where the bias voltage levels are adjusted based on the operational state (startup vs. steady-state). This dynamic control achieves fast startup and improved phase noise performance while keeping the circuit relatively simple by using straightforward voltage level switching rather than complex adaptive control mechanisms.
Data Source
AI summary
Apparatus and methods for back gate biasing of crystal oscillators for enhanced negative resistance are disclosed herein. In certain embodiments, a crystal oscillator includes a crystal and an inverter having an input connected to a first terminal of the crystal and an output connected to a second terminal of the crystal. The inverter includes an n-type metal oxide semiconductor (NMOS) transistor and a p-type metal oxide semiconductor (PMOS) transistor that serve to invert an input oscillation signal from the crystal. The crystal oscillator further includes a back gate bias control circuit that adjusts a negative resistance of the inverter by controlling a back gate bias of at least one of the NMOS transistor or the PMOS transistor.