Crystal Oscillator Feedback Network for Low-Noise Oscillation

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Solution Overview

Problem

Conventional crystal oscillator circuits suffer from noise degradation due to the self-biasing feedback resistor, which is essential for oscillation but adversely affects performance, and removing it can lead to circuit failure.

Innovation Solution

A crystal oscillator design incorporating an inverter, a feedback network with a serial connection of feedback resistors and a clamp network, and shunt capacitors, where the feedback network contributes minimal noise when the circuit is most susceptible, thereby improving performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a self-biasing feedback resistor is used in the crystal oscillator circuit, then oscillation can be maintained, but noise performance deteriorates

Engineering Contradiction:
Improveoscillation functionalityVSAvoidnoise contribution
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts the biasing function from the traditional single self-biasing feedback resistor and separates it into two distinct feedback resistors (first feedback resistor and second feedback resistor) connected in series. This extraction allows the circuit to maintain oscillation functionality while reducing noise, as the biasing function is distributed across two components rather than concentrated in one noisy resistor.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The feedback path is segmented into multiple sections with the first feedback resistor, clamp network, and second feedback resistor arranged in series. This segmentation divides the original single resistor function into distributed components, where each segment contributes less noise individually while collectively maintaining the required biasing and oscillation conditions.

Inventive Principle:
Principle #1Segmentation

2Object-generated harmful factors

If the self-biasing feedback resistor is removed to reduce noise, then noise performance improves, but oscillation fails to occur

Engineering Contradiction:
Improvenoise contributionVSAvoidoscillation functionality
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The clamp network acts as an intermediary element between the first feedback resistor and the second feedback resistor. This intermediary component enables the circuit to maintain proper biasing and sustain oscillation without relying on a single high-value self-biasing resistor that would generate excessive noise. The clamp network mediates the feedback signal to ensure oscillation conditions are met while keeping noise levels low.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the feedback network parameters by using two smaller feedback resistors in series instead of one large self-biasing resistor. This parameter change reduces the noise contribution while maintaining the necessary biasing conditions through the combined effect of the series resistors and the clamp network, enabling oscillation to occur with improved noise performance.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10291180B2Crystal oscillator circuit and method thereof
Publication Date: 2019.05.14 REALTEK SEMICON CORP
  • US10291180B2 patent drawing
  • US10291180B2 patent drawing
  • US10291180B2 patent drawing

AI summary

A crystal oscillator comprises: an inverter configured to receive a first voltage at a first node and output a second voltage at a second node; a feedback network inserted between the first node and the second node, wherein the feedback network includes a serial connection of a first feedback resistor, a clamp network, and a second feedback resistor; a first optional resistor inserted between the second node and a third node; a second optional resistor inserted between a fourth node and the first node; a crystal inserted between the third node and the fourth node; a first shunt capacitor inserted between the third node and a ground node; and a second shunt capacitor inserted between the fourth node to and the ground node.