Variable-Resistance Crystal Oscillator for Lower Phase Noise

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Solution Overview

Problem

Crystal oscillators experience degradation in phase noise performance due to increased load capacitance, which affects the frequency stability and accuracy of clock signals used in devices like RFIC and serial communication devices.

Innovation Solution

A crystal oscillator design that includes a transconductance circuit, load capacitors, and a feedback resistance circuit with a variable resistance controller, which dynamically adjusts the feedback resistance based on the capacitance of the load capacitors to minimize phase noise by reducing the average resistance value during periods where high feedback resistance is not required.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If load capacitance is increased to compensate for frequency change, then frequency stability is improved, but phase noise performance deteriorates

Engineering Contradiction:
Improvefrequency stabilityVSAvoidphase noise
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The feedback resistance is made dynamically adjustable rather than fixed. The variable resistance controller modifies the feedback resistance value in response to changing load capacitance conditions, allowing the system to maintain optimal phase noise performance across different operating conditions while preserving frequency stability compensation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The feedback resistance parameter is changed adaptively based on the load capacitance value. When load capacitance increases (which degrades phase noise), the feedback resistance is adjusted to a lower value to compensate for the phase noise degradation, thereby maintaining overall phase noise performance while preserving the frequency stability benefit of increased load capacitance.

Inventive Principle:
Principle #35Parameter changes

2Object-generated harmful factors

If feedback resistance is increased to reduce phase noise, then phase noise performance is improved, but the average resistance value increases causing other performance degradation

Engineering Contradiction:
Improvephase noiseVSAvoidfrequency characteristic
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The feedback resistance is adjusted periodically or dynamically based on the oscillation cycle and load capacitance conditions. Rather than maintaining a constantly high resistance value, the system applies higher resistance only when needed during specific phases of operation, and reduces it during other phases, thereby achieving phase noise reduction without sustained degradation of frequency characteristics.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The feedback resistance transitions from a static high value to a dynamically controlled variable value. The variable resistance controller adjusts the resistance in real-time based on operating conditions, allowing the system to achieve low average resistance (preserving frequency characteristics) while still providing sufficient resistance during critical phases to reduce phase noise.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11368125B2Crystal oscillator reducing phase noise and semiconductor chip including the same
Publication Date: 2022.06.21 SAMSUNG ELECTRONICS CO LTD
  • US11368125B2 patent drawing
  • US11368125B2 patent drawing
  • US11368125B2 patent drawing

AI summary

A crystal oscillator reducing phase noise and a semiconductor chip including the same are provided. The crystal oscillator includes a transconductance circuit electrically connected to a crystal, a load capacitor connected to the transconductance circuit, a feedback resistance circuit connected between an input terminal of the transconductance circuit and an output terminal of the transconductance circuit, the feedback resistance circuit configured to provide a feedback resistance, and a variable resistance controller configured to generate a resistance control signal for controlling the feedback resistance, the resistance control signal causing the feedback resistance to have a first value in a first period and a second value in a second period, the first value being less than the second value, the first period corresponding to a first portion of a cycle of the clock signal, and the second period corresponding to a second portion of the cycle different from the first portion.