Crystal Oscillator Wakeup Using PLL Chirp Injection
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Solution Overview
Problem
Crystal oscillators face a design trade-off between power efficiency and startup time due to varying crystal resistance, leading to sub-optimal power consumption and extended wake-up times when transitioning from sleep mode to steady-state operation.
Innovation Solution
Implementing a phase-locked loop (PLL) with a chirp mode that uses a retained coarse code and sweep voltage to generate a chirp signal near the target stimulating frequency for the crystal oscillator, facilitating quick transition from sleep mode to steady-state oscillation by configuring the PLL to operate in chirp mode during wake-up and switching to feedback loop regulation once steady state is achieved.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If power is increased to reduce startup time, then startup time is reduced, but power efficiency deteriorates
Solution Approach 1:
The system performs preliminary action by storing a retained coarse code during prior operation that represents the optimal tuning point for the VCO. During wakeup, this pre-stored code is immediately applied to the VCO, eliminating the need for time-consuming frequency search and directly reducing startup time while maintaining power efficiency through targeted energy injection at the correct frequency.
Solution Approach 2:
The invention changes the operational parameters of the PLL by switching between chirp mode (during startup) and feedback loop mode (during steady-state operation). The chirp mode enables rapid frequency sweeping to quickly establish oscillation, while the feedback loop mode optimizes power consumption during normal operation, thus resolving the contradiction between startup speed and power efficiency.
2Reliability
If power is decreased to improve noise performance in steady state, then noise performance is improved, but startup time increases
Solution Approach 1:
The system dynamically adjusts its operational mode based on the startup phase. During the transient startup phase, the PLL operates in chirp mode with higher power to ensure rapid and reliable oscillation establishment. Once steady state is achieved, the system transitions to feedback loop mode with optimized power levels for low noise performance, thus achieving both fast startup and low noise operation at different times.
Solution Approach 2:
The invention implements periodic action through the chirp signal that sweeps through a frequency range to stimulate the crystal oscillator. This periodic frequency modulation quickly establishes oscillation during startup, after which the system transitions to continuous operation at the stable reference frequency, achieving both rapid startup and low noise steady-state performance.
3Use of energy by moving object
If frequency sweeping range is reduced to improve power efficiency, then power consumption is reduced, but frequency acquisition reliability deteriorates
Solution Approach 1:
The system performs preliminary action by pre-determining and storing the retained coarse code that identifies the optimal frequency point. This preliminary frequency identification eliminates the need for extensive frequency sweeping during startup, allowing the system to use a narrow, power-efficient frequency range while maintaining high frequency acquisition reliability through the pre-stored tuning information.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the wake-up time of crystal oscillators while maintaining power efficiency by injecting energy effectively over a smaller frequency range, ensuring rapid stabilization at the target frequency.
Implementation Method 1
Their piezoelectric properties allow them to be a frequency-determining element in electronic circuits. A crystal oscillator, particularly one made of quartz crystal, is distorted by an electric field when voltage is applied to an electrode near or on the crystal.
Implementation Method 2
setting the PLL to an operating mode responsive to detecting the steady state operation of the crystal oscillator, such that, in the normal operating mode, the control voltage of the VCO is regulated by a feedback loop of the PLL as a function of a reference clock signal received at the reference frequency from the crystal oscillator.
Data Source
AI summary
Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.