Hybrid Hardmask Layers for GAA Etch Profile Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in forming gate-all-around (GAA) transistors with effective isolation structures to reduce current leakage from channels to the substrate, particularly in advanced semiconductor devices with complex geometries.
Innovation Solution
The method involves forming a patterned hard mask over a semiconductor stack, using a combination of crystalline and amorphous hard mask layers to prevent profile distortion during etching, and forming isolation structures to minimize electrical connections and enhance the integrity of the GAA transistor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer hard mask is used, then the manufacturing process is simpler, but profile distortion occurs during etching
Solution Approach 1:
The hard mask is divided into multiple layers with different materials and properties. The first hard mask layer provides etch selectivity, while the second hard mask layer maintains structural integrity and prevents profile distortion during etching. This segmentation allows each layer to perform its specific function optimally.
Solution Approach 2:
The patent uses composite hard mask structures combining different materials (e.g., silicon nitride, silicon oxide, tantalum oxide) with complementary properties. The composite structure leverages the high etch selectivity of certain materials while using others to maintain mechanical stability and prevent distortion during the etching process.
2Device complexity
If isolation structures are not formed, then the device fabrication is simpler, but current leakage occurs from channels to substrate
Solution Approach 1:
Isolation structures are formed by removing or replacing certain regions with dielectric materials. The patent extracts conductive paths between channels and substrate by filling trenches with isolation dielectric, effectively taking out the harmful electrical connection while maintaining device functionality.
Solution Approach 2:
Isolation dielectric structures serve as intermediary elements between the channel and substrate, preventing direct electrical contact. These intermediate layers act as mediators that block current leakage while allowing the device to operate normally, separating the channel region from the substrate electrically.
3Productivity
If the hard mask layer is too thin, then the deposition process is faster, but the mask lacks sufficient etching resistance
Solution Approach 1:
The hard mask functionality is segmented across multiple layers with different thicknesses and material compositions. The first layer can be thinner for faster deposition, while the second layer provides additional thickness and material properties to ensure sufficient etching resistance, allowing each layer to be optimized independently.
Solution Approach 2:
The patent employs composite hard mask materials where the first layer may use a material with high deposition speed, while the second layer uses a material with superior etch resistance. This composite approach allows the overall structure to achieve both fast deposition and adequate etching protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the electrical performance of GAA transistors by reducing unwanted electrical connections and maintaining structural integrity, thereby enhancing the reliability and efficiency of semiconductor devices.
Implementation Method 1
crystallizing the first hard mask layer to form a crystalline hard mask layer
Implementation Method 2
depositing an amorphous hard mask layer over the crystalline hard mask layer
Data Source
AI summary
A semiconductor device includes a substrate, first and second semiconductor strips, a dummy fin structure, first and second channel layers, a gate structure, and crystalline and amorphous hard mask layers. The first and second semiconductor strips extend upwardly from the substrate and each has a length extending along a first direction. The dummy fin structure is laterally between the first and second semiconductor strips. The first and second channel layers extend in the first direction above the first and second semiconductor strips and are arranged in a second direction substantially perpendicular to the substrate. The crystalline hard mask layer extends upwardly from the dummy fin structure and has an U-shaped cross section. The amorphous hard mask layer is in the crystalline hard mask layer. The amorphous hard mask layer has an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.