Crystalline Interfacial Passivation for III-V HEMT Reliability
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Solution Overview
Problem
Current methods for passivating III-V semiconductor compounds in HEMTs result in high interfacial density of states, leading to device performance issues such as drain current degradation and threshold voltage fluctuations.
Innovation Solution
The method involves epitaxially growing buffer and III-V compound layers, in-situ treating native oxide layers to form crystalline oxide layers, and forming crystalline interfacial and dielectric passivation layers to reduce interfacial density of states, thereby improving the reliability and performance of HEMTs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional passivation methods are used on III-V compounds, then the surface is protected from ambient air reaction, but the interfacial density of states becomes undesirably high causing device performance degradation
Solution Approach 1:
A crystalline interfacial layer is formed on the III-V compound surface before the passivation layer is applied. This preliminary crystalline structure reduces the interfacial density of states and prevents the formation of high-density amorphous interfaces that would otherwise occur with conventional direct passivation methods
Solution Approach 2:
The patent changes the structural parameter of the interface from amorphous to crystalline by forming a crystalline interfacial layer. This parameter change significantly reduces the interfacial density of states while maintaining effective surface protection against ambient air reaction
2Ease of manufacture
If conventional passivation is applied directly to III-V compounds, then manufacturing is simplified, but threshold voltage fluctuation and off-current leakage increase
Solution Approach 1:
The crystalline interfacial layer is formed as a preliminary step before passivation, creating a stable interface that reduces threshold voltage fluctuation and off-current leakage while maintaining manufacturing feasibility through integrated process steps
3Reliability
If amorphous native oxide layers are left on III-V compounds, then the surface is naturally passivated, but device performance degrades due to high interfacial density of states
Solution Approach 1:
The patent transforms the amorphous native oxide layer into a crystalline interfacial layer through controlled formation processes. This parameter change from amorphous to crystalline structure maintains natural passivation while dramatically improving interface quality and reducing interfacial density of states
Solution Approach 2:
The native oxide layer, which would normally be considered a harmful defect causing high interfacial density of states, is converted into a beneficial crystalline interfacial layer that provides both protection and low interface states when properly formed and integrated into the device structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces interfacial density of states, stabilizes threshold voltage, and enhances the reliability and performance of HEMTs by converting amorphous native oxide layers into crystalline structures within the HEMT manufacturing process.
Implementation Method 1
in-situ treating native oxide layers to form crystalline oxide layers
Implementation Method 2
epitaxially growing buffer and III-V compound layers
Data Source
AI summary
A semiconductor device includes a compound semiconductor layer comprising a III-V material; a first layer on the compound semiconductor layer and comprising oxygen, nitrogen, and a material included in the compound semiconductor layer; a second layer over the first layer, wherein at least a portion of the second layer comprises a single crystalline structure or a polycrystalline structure; a dielectric layer over the second layer; and a source/drain electrode extending through the dielectric layer, the second layer, and the first layer and into the compound semiconductor layer.