Crystalline Interlayer Passivation for III-V Semiconductor Interface States

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Solution Overview

Problem

III-V compound semiconductors used in MOSFETs and other semiconductor devices suffer from a high density of interface states between the III-V compound semiconductor material layer and a high k dielectric material layer, which compromises the crystallinity and mobility of the channel region.

Innovation Solution

A thin crystalline interlayer is formed on the surface of a single crystal III-V compound semiconductor material layer to act as a passivation layer, reducing and eliminating the density of interface states by protecting the crystallinity of the III-V compound semiconductor material layer before further processing, and a high k dielectric material layer is then formed on top of this interlayer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a high k dielectric material layer is formed directly on the III-V compound semiconductor material layer, then the device structure is simplified, but the density of interface states increases significantly

Engineering Contradiction:
Improvedevice structureVSAvoiddensity of interface states
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

A crystalline interlayer is introduced as an intermediary between the III-V compound semiconductor material layer and the high k dielectric material layer. This interlayer acts as a mediator that prevents direct interaction between the dielectric material and the semiconductor surface, thereby eliminating the formation of interface states while maintaining structural simplicity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If chemical pre-treatment or amorphous Si passivation is applied to the III-V compound semiconductor surface, then some interface state reduction is achieved, but the density of interface states remains above 1E12/cm2ev

Engineering Contradiction:
Improvedensity of interface statesVSAvoidcrystallinity of surface atoms
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the physical and chemical parameters of the passivation layer by using a crystalline material instead of amorphous Si, and by controlling the deposition process to maintain crystalline structure. This parameter change enables the passivation layer to preserve the crystallinity of underlying surface atoms while achieving superior interface state reduction below 1E12/cm2ev.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8809860B2III-V compound semiconductor material passivation with crystalline interlayer
Publication Date: 2014.08.19 GLOBALFOUNDRIES US INC
  • US8809860B2 patent drawing
  • US8809860B2 patent drawing
  • US8809860B2 patent drawing

AI summary

The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.