Crystalline Semiconductor Pattern Fabrication via Seed Layer Crystallization
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Solution Overview
Problem
Current semiconductor device fabrication methods, particularly those using silicon-on-insulator (SOI) substrates, face challenges such as complex processes, defects, and void generation due to high temperature thermal treatments, which affect the quality and integration density of semiconductor devices.
Innovation Solution
A method involving the formation of a preliminary active pattern with alternately stacked barrier and non-single crystal semiconductor layers on a semiconductor substrate, followed by crystallization using the substrate as a seed layer, and subsequent removal of a sacrificial crystalline semiconductor layer to create a crystalline semiconductor pattern with the same crystal structure as the substrate, along with the formation of gate and source/drain structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SIMOX method is used to form SOI substrate, then a buried insulating layer is formed, but the process becomes complicated and defects are generated inside the semiconductor substrate
Solution Approach 1:
The invention divides the semiconductor structure into distinct segments: a semiconductor substrate, a buried insulating layer, and a crystalline semiconductor layer. This segmentation allows each layer to be optimized independently, avoiding the need for complex SIMOX processes while maintaining substrate quality and reducing defect generation.
Solution Approach 2:
The invention performs preliminary actions by forming the buried insulating layer and crystalline semiconductor layer in a predetermined sequence before fabricating the semiconductor elements. This preliminary structuring simplifies subsequent fabrication processes compared to SIMOX, where complex thermal treatments and ion implantation are required after substrate preparation.
2Reliability
If two substrates are attached at high temperature to form SOI, then an insulating layer is formed, but voids are generated at the junction portion and thermal treatment complexity increases
Solution Approach 1:
The invention uses an intermediary approach by forming the buried insulating layer as a separate layer between the semiconductor substrate and the crystalline semiconductor layer, rather than directly attaching two substrates. This eliminates the need for high-temperature substrate attachment and prevents void formation at junction portions.
Solution Approach 2:
The invention creates a crystalline semiconductor layer that copies the crystal structure of the semiconductor substrate, ensuring lattice matching and reducing defects. This copying approach achieves the desired insulating structure without requiring complex high-temperature substrate attachment processes.
3Productivity
If channel length is reduced for high integration, then integration density increases, but leakage current and junction capacitance increase due to impurity concentration
Solution Approach 1:
The invention applies local quality by forming a crystalline semiconductor layer with specific crystal orientation and structure in the channel region, while maintaining different impurity concentration profiles in source/drain regions. This local optimization allows high integration density with controlled leakage current and junction capacitance.
Solution Approach 2:
The invention uses composite material structure combining a semiconductor substrate, buried insulating layer, and crystalline semiconductor layer with optimized crystal orientation. This composite structure enables reduced channel length for high integration while controlling leakage current through the specific crystallographic relationship between layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of semiconductor devices with improved crystal structure matching and reduced defects, allowing for enhanced performance and integration density while minimizing the complexity and thermal treatment-related issues of existing methods.
Implementation Method 1
By crystallizing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern, using the semiconductor substrate as a seed layer, the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern are changed to a sacrificial crystalline semiconductor layer and a crystalline semiconductor pattern, respectively
Data Source
AI summary
In one embodiment, a method of fabricating a semiconductor device having a crystalline semiconductor layer includes preparing a semiconductor substrate and forming a preliminary active pattern on the semiconductor substrate. The preliminary active pattern includes a barrier pattern and a non-single crystal semiconductor pattern. A sacrificial non-single crystal semiconductor layer covers the preliminary active pattern and the semiconductor substrate. By crystallizing the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern, using the semiconductor substrate as a seed layer, the sacrificial non-single crystal semiconductor layer and the non-single crystal semiconductor pattern are changed to a sacrificial crystalline semiconductor layer and a crystalline semiconductor pattern, respectively. The crystalline semiconductor pattern and the barrier pattern constitute an active pattern. The sacrificial crystalline semiconductor layer is removed.