Crystalline Semiconductor Formation on Thin SOI Templates
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is the difficulty in forming crystalline semiconductor materials on very thin templates without material irregularities, such as agglomeration, which limits the further reduction of transistor dimensions and increases parasitic capacitance, especially in fully depleted SOI transistor elements.
Innovation Solution
A method involving the deposition of an amorphous semiconductor layer on a crystalline template, followed by a radiation-based anneal process that controls heat penetration to melt only the surface layers, preserving a stable bottom layer and allowing crystallization upon cooling, thereby forming high-quality crystalline semiconductor material even with reduced template thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional epitaxial growth techniques are used on very thin crystalline template material (thickness < 10 nm), then crystalline semiconductor material can be formed, but material irregularities such as agglomeration occur that prevent required growth
Solution Approach 1:
The patent changes the fundamental parameter of crystallization method from conventional epitaxial growth to laser annealing of amorphous semiconductor material. This parameter change allows processing of very thin template materials (5-50 nm) without the agglomeration problems that plague epitaxial growth on such thin templates, thereby resolving the contradiction between material quality and process feasibility
Solution Approach 2:
The patent replaces the thermal field-based epitaxial growth process with a laser-based annealing process. The laser provides localized, controlled energy input that melts and recrystallizes the amorphous semiconductor material without causing the material irregularities associated with conventional epitaxial growth on thin templates, thus resolving the contradiction
2Speed
If the thickness of the crystalline template material is reduced to enable fully depleted transistor elements, then parasitic capacitance is reduced and operating speed increases, but forming drain and source regions with high dopant concentration becomes extremely difficult
Solution Approach 1:
The patent performs preliminary deposition of amorphous semiconductor material onto the thin crystalline template before attempting to form drain and source regions. This preliminary action creates a thicker, more manageable semiconductor layer (5-50 nm total) that can be easily doped using conventional ion implantation or in-situ doping techniques, thereby resolving the contradiction between achieving fully depleted operation and enabling easy doping
Solution Approach 2:
The patent segments the semiconductor structure into multiple layers: a thin crystalline template layer (5-50 nm) that provides the fully depleted channel, and an overlying amorphous semiconductor layer that serves as the doped drain and source regions. This segmentation allows each layer to fulfill its specific function optimally, resolving the contradiction between speed and manufacturability
3Manufacturing precision
If laser annealing is used to form crystalline material on thin templates, then material irregularities are reduced and crystalline quality is improved, but precise control of heat penetration depth is required to preserve the bottom layer
Solution Approach 1:
The patent employs pulsed laser annealing instead of continuous heating. The periodic pulsed action allows precise control of heat penetration depth by adjusting pulse duration and repetition rate, enabling the laser energy to be confined to specific depth ranges and thus preserving the bottom crystalline template layer while crystallizing the overlying amorphous material, resolving the contradiction between quality and control complexity
Solution Approach 2:
The patent uses dynamic control of laser parameters (wavelength, pulse duration, energy density, scanning speed) to adapt the heat penetration depth to the specific thickness of the amorphous layer being processed. This dynamic adjustment capability allows precise control over which layers are melted and recrystallized, resolving the contradiction between achieving high crystalline quality and managing process control complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of crystalline semiconductor materials with precise control over thickness, reducing material irregularities and allowing for the creation of sophisticated transistor elements with reduced dimensions and improved performance by maintaining a stable crystalline structure and minimizing dopant diffusion.
Implementation Method 1
exposing the amorphous semiconductor layer to radiation having a wavelength of 380 nm or less, so as to melt the amorphous semiconductor layer and a surface layer of the crystalline semiconductor base layer
Implementation Method 2
appropriately restricting a 'penetration' depth of heat into the lower-lying template material, thereby also efficiently restricting the depth to which a melting of the template material may be initiated
Implementation Method 3
cooling the amorphous semiconductor layer and the surface layer so as to form a converted crystalline semiconductor material from the amorphous semiconductor layer and the surface layer
Data Source
AI summary
A method of forming a crystalline semiconductor material on the basis of a very thin semiconductor base material and an amorphous semiconductor material deposited thereon is disclosed. Radiation-based anneal process techniques may be applied by using appropriate radiation wavelengths, for instance, below 380 nm, in order to efficiently restrict energy deposition to the surface-near area. A solid and crystalline bottom portion of the semiconductor base material may be reliably preserved, thereby achieving crystallization of the overlying material portions and, in particular, of the previously deposited amorphous semiconductor material. Extremely thin channel regions of fully depleted SOI transistor elements may be used as a semiconductor base material, upon which raised drain and source regions may be formed in a later manufacturing stage, thereby substantially avoiding any process irregularities, which are conventionally associated with the epitaxial growth of a semiconductor material on a very thin semiconductor base material.