Crystalline SiN Passivation for III-N Devices
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Solution Overview
Problem
III-N semiconductor devices face challenges in achieving optimal passivation and gate dielectric performance due to the thickness and crystallinity of Silicon Nitride (SiN) layers, which affect transconductance and threshold voltage, necessitating improved interface properties and control over SiN growth.
Innovation Solution
A III-N layer stack with a fully crystalline SiN passivation layer, doped with Al or B, is used to enhance interface quality and maintain epitaxial growth, ensuring better control over thickness and reducing dangling bonds, thereby improving passivation and gate dielectric performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick SiN layer is used for passivation, then passivation performance is improved, but device complexity increases due to the need for selective etching processes
Solution Approach 1:
The SiN passivation layer is segmented into two distinct layers: a first SiN layer (3-10 nm thick) that serves as gate dielectric, and a second SiN layer (10-200 nm thick) that provides passivation. This segmentation allows each layer to be optimized for its specific function and enables selective etching of the second layer without affecting the first layer, thus resolving the contradiction between passivation performance and process complexity
Solution Approach 2:
Different regions of the device receive different treatments: the gate area retains both SiN layers for optimal electrical performance, while other areas may have the second SiN layer selectively removed for passivation only. This local differentiation allows the device to achieve both good passivation performance and simplified processing in non-critical areas
2Reliability
If a thick SiN layer is used as gate dielectric, then leakage current is reduced, but transconductance decreases due to reduced capacitive coupling
Solution Approach 1:
The gate dielectric function is segmented from the passivation function into two separate SiN layers. The first SiN layer (3-10 nm) is optimized for gate dielectric performance with thin thickness to maintain capacitive coupling and high transconductance, while the second SiN layer (10-200 nm) provides passivation without affecting electrical performance. This resolves the contradiction between leakage current reduction and transconductance maintenance
Solution Approach 2:
The first SiN layer acts as an intermediary between the gate and the second SiN layer, providing the necessary electrical insulation and capacitive coupling while allowing the second layer to provide passivation. This intermediary structure enables both functions to coexist without compromising either performance metric
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in improved transconductance, reduced threshold voltage, and enhanced resistance to dry etching, leading to more reliable and efficient semiconductor devices with improved electrical parameters.
Implementation Method 1
TEM has revealed the first few monolayers of SiN grow epitaxially onto the (In)AlGaN barrier layer
Implementation Method 2
the passivation layer comprises a fully crystalline sub layer at the Al-III-N interface and at least part of the fully crystalline sub layer comprises Al or B
Data Source
AI summary
A device comprising a III-N layer stack featuring a two-dimensional electron gas is disclosed, comprising: —a III-N layer; —a AI-III-N layer on top of the III-N layer; —a passivation layer on top of said AI-III-N layer, the passivation layer comprising Silicon Nitride (SiN); wherein said passivation layer comprises a fully crystalline sub layer at the AI-III-N interface and at least part of the fully crystalline sub layer comprises Al and/or B; and associated methods for manufacturing the device.