Crystallized Gate Dielectric Structures for Selective Etching
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, the etch rate of gate dielectric layers during the formation of transistor structures becomes a challenge, leading to increased losses and reduced performance due to the lack of etching selectivity from work function tuning layers.
Innovation Solution
A crystallization process is applied to the gate dielectric layers to decrease their etch rate relative to the etching processes used for patterning work function tuning layers, thereby reducing losses and improving the selectivity and performance of the gate dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but etching selectivity deteriorates leading to increased gate dielectric layer losses
Solution Approach 1:
The patent applies a crystallization process to change the physical state of the gate dielectric layer from amorphous to crystalline, which fundamentally alters its etching characteristics. This parameter change in the material structure enables the gate dielectric layer to withstand subsequent etching processes with minimal loss, thereby resolving the contradiction between maintaining high integration density and reducing material losses during fabrication.
Solution Approach 2:
The crystallization process is performed in advance, before the etching of work function tuning layers occurs. This preliminary action prepares the gate dielectric layer to be more resistant to etching, ensuring that when the etching process occurs later in the fabrication sequence, the gate dielectric layer suffers minimal loss despite the reduced feature sizes required for high integration density.
2Reliability
If etching processes are used to pattern work function tuning layers, then transistor performance can be optimized, but gate dielectric layer losses increase due to poor etching selectivity
Solution Approach 1:
By changing the crystalline structure of the gate dielectric layer through a dedicated crystallization process, the material's resistance to etching is significantly enhanced. This allows the etching process to effectively pattern the work function tuning layers for optimal transistor performance while the gate dielectric layer remains substantially intact, thus resolving the contradiction between achieving good transistor performance and minimizing gate dielectric layer losses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The crystallization process enhances the etching selectivity of gate dielectric layers, minimizing losses during etching and improving the overall performance of the resulting semiconductor devices by reducing leakage current.
Implementation Method 1
a crystallization process is performed to decrease the etch rate of the gate dielectric layers
Data Source
AI summary
In an embodiment, a device includes: a first gate dielectric on a first channel region of a first semiconductor feature; a first gate electrode on the first gate dielectric; a second gate dielectric on a second channel region of a second semiconductor feature, the second gate dielectric having a greater crystallinity than the first gate dielectric; and a second gate electrode on the second gate dielectric.