Crystallized Gate Dielectrics for Selective Transistor Gate Etching
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Solution Overview
Problem
As the minimum feature sizes in semiconductor devices are reduced, challenges arise in maintaining the integrity and performance of gate dielectric layers during etching processes, leading to increased etch rates and potential losses of these critical layers.
Innovation Solution
A crystallization process is performed on the gate dielectric layers to decrease their etch rate relative to the etching processes used for patterning work function tuning layers, thereby reducing losses and improving selectivity during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but the etch rate of gate dielectric layers increases leading to potential losses during etching processes
Solution Approach 1:
The patent applies parameter changes by modifying the physical and chemical properties of the gate dielectric layer through crystallization treatment. This process alters the etch rate parameter of the gate dielectric layer, making it more resistant to etching while maintaining the reduced feature size geometry. The crystallization transforms the dielectric material's structure to achieve the desired etch resistance without changing the device dimensions.
Solution Approach 2:
The crystallization process is performed as a preliminary action before the etching of work function tuning layers. By pre-treating the gate dielectric layer to enhance its etch resistance, the patent ensures that subsequent etching processes will not cause excessive loss of the gate dielectric layer. This preliminary modification of material properties prevents the harmful effect of dielectric layer loss during later fabrication steps.
2Ease of manufacture
If conventional etching processes are used for patterning work function tuning layers, then the etching process can proceed, but selectivity between gate dielectric layers and work function tuning layers deteriorates leading to increased gate dielectric layer loss
Solution Approach 1:
The patent changes the etch rate parameter of the gate dielectric layer through crystallization, creating a parameter difference between the gate dielectric layer and the work function tuning layer. This parameter modification establishes proper etching selectivity, allowing the etching process to selectively remove work function tuning layer material while preserving the gate dielectric layer. The crystallized dielectric layer's modified properties enable it to withstand the etching conditions that would otherwise cause excessive loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The crystallization process enhances the etching selectivity of gate dielectric layers, reduces losses during etching, and improves the overall performance of semiconductor devices by minimizing leakage current.
Implementation Method 1
a crystallization process is performed to decrease the etch rate of the gate dielectric layers
Data Source
AI summary
In an embodiment, a device includes: a first gate dielectric on a first channel region of a first semiconductor feature; a first gate electrode on the first gate dielectric; a second gate dielectric on a second channel region of a second semiconductor feature, the second gate dielectric having a greater crystallinity than the first gate dielectric; and a second gate electrode on the second gate dielectric.