Chip Scale Package Hard Board Wiring Without Plated Through Holes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional chip scale packages face issues with electrical connection reliability due to chip deviation and encapsulant overflow during the molding process, leading to poor electrical connections and increased fabrication costs, especially when trying to stack semiconductor packages without plated through holes (PTHs).
Innovation Solution
A chip scale package using a hard board with conductive elements and an encapsulating layer, where the electronic component is attached to the hard board via a die attach film, and a dielectric and wiring layer are formed to eliminate the need for PTHs, ensuring reliable electrical connections and reducing fabrication costs by avoiding warpage and adhesive residue issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a soft adhesive film is used to attach the chip, then the chip can be easily mounted, but the chip deviates due to film-softening and extension during the molding process, adversely affecting electrical connection
Solution Approach 1:
The patent changes the physical state of the support structure from soft (adhesive film) to hard (carrier board with rigid support). This parameter change prevents film-softening and extension during molding, eliminating chip deviation while maintaining ease of mounting through the structured carrier design.
Solution Approach 2:
The patent uses a disposable adhesive layer applied to the carrier board, which is replaced with each new chip mounting. This allows the use of strong adhesion for mounting while the adhesive itself is consumed and discarded, separating the mounting function from the structural support function.
2Productivity
If the adhesive film is softened by heat in the molding process, then the molding can be completed, but encapsulant overflow occurs to the active surface of the chip, contaminating the electrode pads and resulting in poor electrical connection
Solution Approach 1:
The patent introduces a carrier board as an intermediary structure between the chip and the molding process. The carrier board with its rigid structure and controlled cavity prevents encapsulant from reaching the chip's active surface, while still allowing the molding process to proceed normally through heat and pressure application.
Solution Approach 2:
The patent employs preliminary protective measures by designing the carrier board structure to preemptively block the path of encapsulant flow before it can reach the electrode pads. The raised edges and controlled cavity create a physical barrier that prevents contamination before it occurs.
3Stability of the object's composition
If a hard carrier is used to secure the encapsulant, then warpage is reduced, but the process is complicated and fabrication cost increases, and adhesive residue remains on the encapsulant after carrier removal
Solution Approach 1:
The patent merges the carrier board with the final package structure, making the carrier become part of the encapsulated assembly. This eliminates the need for carrier removal and prevents adhesive residue issues, while the integrated structure maintains warpage control throughout the process.
Solution Approach 2:
The patent transforms the carrier from a temporary tool to be discarded into a permanent structural element that is retained in the final package. This recovering approach eliminates the complications of carrier removal while maintaining the stability benefits of the rigid support structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a reliable electrical connection between chip electrode pads and the wiring layer, enhances product reliability, and allows for stacked semiconductor packages without PTHs, reducing fabrication costs and simplifying the process.
Implementation Method 1
an adhesive film 11 is prepared, and a plurality of chips 12, each having an active surface 121 and an opposite inactive surface 122, is provided and attached to the adhesive film 11 via the active surfaces 121 thereof
Implementation Method 2
a molding process is performed to form an encapsulant 13 such as an epoxy resin encapsulating the inactive surfaces 122 and side surfaces of the chips 12
Data Source
AI summary
A CSP includes: a hard board having a first wiring layer with conductive pads; a plurality of conductive elements disposed on at least a portion of the conductive pads; an electronic component having opposite active and inactive surfaces and being mounted on the hard board via the inactive surface; an encapsulating layer disposed on the hard board for encapsulating the conductive elements and electronic component, the active surface of the electronic component and the surfaces of the conductive elements being exposed through the encapsulating layer; a first dielectric layer and a third wiring layer disposed on the encapsulating layer, the third wiring layer being electrically connected to the conductive elements and the electronic component and further electrically connected to the first wiring layer through the conductive elements, thereby obtaining a stacked connection structure without the need of PTHs and using the hard board as a main structure to avoid warpage.