Chip Scale Package Fabrication Using Mold Compound Encapsulation
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Solution Overview
Problem
Current chip scale package fabrication methods are costly and prone to reliability issues due to exposed semiconductor die portions, which can be damaged during handling or exposed to moisture, limiting their long-term reliability and cost-effectiveness.
Innovation Solution
A method involving the addition of conductive bumps, precise sawing and molding steps to create chip scale packages, where conductive bumps are added to contact locations on a wafer, followed by molding and grinding processes to protect and isolate the semiconductor devices, ensuring reliable contact and protection from environmental factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional lead frame packages are used, then structural support and electrical connection are provided, but the package size is limited by the lead frame dimensions
Solution Approach 1:
The patent removes the traditional lead frame structure from the package design. Instead of using a metal lead frame for support and electrical connection, the invention uses direct wire bonds from the semiconductor die to external terminals, eliminating the lead frame component entirely and enabling smaller package dimensions.
Solution Approach 2:
The patent transitions from a two-dimensional lead frame layout to a three-dimensional packaging structure. The semiconductor die is mounted vertically with wire bonds extending upward to external terminals, utilizing vertical space to reduce the horizontal footprint and overall package size.
2Volume of moving object
If chip scale packages with exposed die portions are used, then packaging size is reduced, but reliability decreases due to exposure to environmental factors
Solution Approach 1:
The patent uses a mold compound encapsulation that completely covers the semiconductor die and internal wire bonds, creating a protective shell that seals the internal components from environmental factors such as moisture and contamination, thereby improving reliability while maintaining small package size.
Solution Approach 2:
The patent employs a composite packaging structure combining the semiconductor die, wire bonds, mold compound encapsulation, and external terminals. This multi-material approach provides both mechanical protection and environmental sealing, enhancing device reliability without increasing package size.
3Volume of moving object
If complicated processing techniques and expensive materials are used for CSP fabrication, then package size is reduced, but manufacturing cost increases
Solution Approach 1:
The patent employs a modular packaging approach where the semiconductor die is separately fabricated and then mounted onto a package substrate. This segmentation allows for standardized, cost-effective manufacturing processes for each component, reducing overall fabrication complexity and cost while achieving small package size.
Solution Approach 2:
The patent uses a universal package substrate design that can accommodate different semiconductor die types and sizes. The same basic package structure, wire bond process, and mold compound encapsulation can be applied across multiple product lines, reducing tooling costs and manufacturing complexity.
Data Source
AI summary
Embodiments of the present invention includes a method of assembling a chip scale package (CSP). The method comprises adding bumps, sawing the saw streets from the front of a wafer, molding the front of the wafer, grinding the back of the wafer, sawing the saw streets from the back of the wafer, molding the back of the wafer, and sawing between devices to form a plurality of packaged devices. Sawing the saw streets from the front of the wafer establishes a first cut. Molding the front of the wafer includes using a first mold compound such that the mold compound fills in the first cut. Sawing the saw streets from the back of the wafer establishes a second cut.