Corner Stress Relief Probe Pads for Post-Dicing Parametric Testing
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Solution Overview
Problem
After dicing, semiconductor chips cannot be accurately tested for parametric parameters, as the probe pads and DUTs in the scribe line regions are destroyed, making it impossible to predict the yield of functional integrated circuits.
Innovation Solution
A semiconductor chip design with a corner stress relief region that includes probe pads on the CSR region, allowing for parametric testing after dicing, where the probe pads are constructed using stacked metal features and via pillars, and an enhanced structure connects the seal ring to the CSR region to distribute stress, preventing damage during backend processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If probe pads are placed in the scribe line region for testing, then parametric testing can be performed before dicing, but the probe pads and DUTs are destroyed during the dicing process, making post-dicing testing impossible
Solution Approach 1:
The probe pads are extracted from the scribe line region and relocated to the corner stress relief region, which remains intact after dicing. This allows the testing function to be separated from the sacrificial scribe line area, enabling post-dicing parametric testing and yield prediction.
Solution Approach 2:
The testing functionality is moved from the horizontal plane (scribe line region) to a different location on the chip (corner stress relief region), utilizing spatial repositioning to preserve test access after the dicing process.
2Strength
If the seal ring structure is present to protect the chip, then chip edge cracks are prevented, but stress concentration may occur during backend processing
Solution Approach 1:
The corner stress relief region is created as a segmented area with reduced seal ring structure, dividing the continuous seal ring into sections. This segmentation allows stress to be distributed differently, preventing concentration at critical corners while maintaining overall chip protection.
Solution Approach 2:
The seal ring structure is modified locally at the corner regions to create stress relief areas, while maintaining the protective function in other regions. This localized modification reduces stress concentration without compromising overall chip integrity.
3Measurement precision
If additional test structures are added to the chip, then post-dicing parametric testing is enabled, but extra space is consumed that could be used for functional circuits
Solution Approach 1:
The corner regions, which are typically sacrificial areas removed or damaged during dicing, are converted into beneficial test regions. By placing probe pads in the corner stress relief region that survives dicing, the previously wasted space becomes functional testing area, enabling post-dicing testing without encroaching on functional circuit space.
Data Source
AI summary
A semiconductor chip includes a corner stress relief (CSR) region. An enhanced structure connects sides of a seal ring structure to surround the CSR region. A device under test (DUT) structure is disposed on the CSR region. A set of probe pad structures is disposed on the CSR region. Two of the set of probe pad structures are electrically connect to the DUT structure.