CT Delta-Sigma ADC Bandwidth Programming for Low-Power Multi-Rate RX
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Solution Overview
Problem
Existing analog to digital converters (ADCs) face challenges in efficiently supporting a wide range of data rates from sub-kilobits per second to megabits per second while maintaining power efficiency and small size, particularly in radio receiver applications like Bluetooth Low Energy and Zigbee standards.
Innovation Solution
The ADC is configured to operate at different data rates by enabling or disabling a negative-R compensation circuit within the delta sigma modulator, allowing for loop gain enhancement and adjustable noise transfer functions, which reduces thermal noise and power consumption by scaling resistor values and capacitor sizes based on data rate requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the ADC is designed to support a wide range of data rates from sub-kilobits per second to megabits per second, then the adaptability is improved, but the device complexity increases
Solution Approach 1:
The patent implements a universal ADC architecture that can operate across multiple data rates (from sub-kilobits per second to megabits per second) by enabling a single converter to perform multiple functions. The delta-sigma modulator is designed with configurable parameters including oversampling ratio and feedback filter coefficients that can be adjusted to support different radio standards (Bluetooth Low Energy, Zigbee, and other proprietary standards), eliminating the need for multiple dedicated ADCs for different data rate requirements
Solution Approach 2:
The ADC employs dynamic configuration capabilities where key parameters such as the oversampling ratio (OSR), feedback filter coefficients, and negative-R compensation circuit settings can be adjusted in real-time based on the operating data rate. This dynamic adaptability allows the same hardware structure to optimize its performance for different data rates, maintaining low complexity while achieving wide versatility across sub-kilobit to megabit per second ranges
2Measurement precision
If the negative-R compensation circuit is enabled for high data rate operation, then the measurement precision is improved, but the power consumption increases
Solution Approach 1:
The negative-R compensation circuit is implemented with dynamic enabling/disabling control based on the operating data rate. For high data rate operations where enhanced precision is required, the circuit is enabled to improve measurement accuracy. For low data rate operations, the circuit is disabled to minimize power consumption, achieving an optimal balance between precision and energy usage across different operating conditions
Solution Approach 2:
The patent changes the operational parameters of the negative-R compensation circuit based on the data rate requirements. By adjusting whether the circuit is enabled or disabled, and by scaling resistor values and capacitor sizes according to data rate requirements, the system optimizes the trade-off between measurement precision and power consumption for each operating mode
3Use of energy by moving object
If resistor values and capacitor sizes are scaled down for low data rate operation, then the power consumption is reduced, but the measurement precision deteriorates
Solution Approach 1:
The feedback filter coefficients and other critical parameters are dynamically adjusted based on the operating data rate. When operating at low data rates with scaled-down components, the system compensates by adjusting the feedback filter coefficients to maintain measurement precision. This dynamic parameter adjustment ensures that conversion accuracy is preserved even when physical component sizes are reduced to minimize power consumption
Data Source
AI summary
A continuous-time (CT) delta-sigma modulator (DSM) based analog to digital converter (ADC) in a radio receive chain supports a wide range of data rates in a power efficient way in a small die area. The ADC utilizes a 2nd order loop-filter with a single-amplifier loop-filter topology using a two stage Miller amplifier with a feed forward path and a push-pull output stage. High bandwidth operations utilize a “negative-R” compensation scheme at the amplifier input. Negative-R assistance is disabled for low data rate applications. With the negative-R assistance disabled, loop-filter resistor values are increased, instead of only the loop filter capacitor values to scale the noise transfer function (NTF), thereby limiting the capacitor area needed and enabling lower power operation. The NTF zero location is programmable allowing the NTF zero to be located near the intermediate frequency for different bandwidths to reduce the DSM quantization noise contribution for narrow-band (low data rate) applications.