CT Delta-Sigma Modulator Using Pipelined SAR Quantization
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Solution Overview
Problem
Existing continuous-time delta-sigma modulators (CT-DSMs) face challenges in increasing the number of quantizer bits without increasing circuit complexity.
Innovation Solution
A CT-DSM design incorporating a loop filter, pipelined successive-approximation register analog-to-digital converter (SAR ADC), feedback circuit, excess loop delay compensation circuit, and logic circuit, which generates multiple digital codes and compensation signals to enhance quantization accuracy without adding complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of quantizer bits is increased to improve measurement precision, then the circuit complexity increases
Solution Approach 1:
The quantization process is divided into multiple stages using a pipelined SAR ADC structure. Instead of using a single high-resolution quantizer, the system segments the quantization into multiple lower-resolution stages, each handling a portion of the total quantization bits. This segmentation allows achieving high overall precision while keeping each individual stage's circuit complexity manageable.
Solution Approach 2:
An excess loop delay (ELD) compensation circuit is introduced as an intermediary component to compensate for the delay effects in the feedback path. This compensation circuit enables the system to maintain accuracy without requiring additional complex quantization stages, thus improving precision without proportionally increasing circuit complexity.
2Reliability
If more quantizer bits are used to improve performance, then the device complexity increases
Solution Approach 1:
The modulator performance is improved by segmenting the high-bit quantization into multiple parallel lower-bit quantizers in the pipelined structure. Each quantizer handles a specific bit range, and their results are combined to achieve the overall high-resolution performance without requiring a single complex high-bit quantizer circuit.
Solution Approach 2:
The system performs preliminary quantization in earlier pipeline stages, converting the input signal into multiple digital codes that represent different bit ranges. This preliminary action allows subsequent stages to work with already-partially-quantized data, reducing the complexity burden on later stages while maintaining overall performance.
3Measurement precision
If the quantization precision is improved by increasing bits, then the number of circuit elements increases
Solution Approach 1:
Multiple quantizer outputs and feedback paths are merged into a unified processing structure. The pipelined SAR ADC combines multiple quantization results through a logic circuit that integrates the digital codes from different stages, reducing the total number of separate circuit elements compared to having completely independent high-resolution quantizers.
Solution Approach 2:
The feedback circuit serves multiple functions simultaneously: it provides feedback signals to the loop filter, generates compensation signals for ELD correction, and supplies signals to multiple quantizer stages. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby improving precision without proportionally increasing the number of circuit elements.
Data Source
AI summary
A continuous-time delta-sigma modulator (CT-DSM) includes a loop filter, a pipelined successive-approximation register analog-to-digital converter (SAR ADC), a feedback circuit, an excess loop delay (ELD) compensation circuit, and a logic circuit. The loop filter generates a first intermediate signal according to an input signal, a feedback signal, and a compensation signal. The pipelined SAR ADC generates a first digital code, a second digital code, a first quantization error signal, and a second quantization error signal according to the first intermediate signal. The feedback circuit generates the feedback signal according to the first digital code, the first quantization error signal, and the second quantization error signal. The ELD compensation circuit generates the compensation signal according to at least one output signal of the feedback circuit. The logic circuit generates an output digital code according to the first digital code and the second digital code.