CT Pipelined VCO ADC Architecture for Bandwidth and Resolution
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Solution Overview
Problem
VCO ADCs have limited bandwidth and performance due to inherent non-linearity and noise shaping, while traditional CT pipelined ADCs face challenges with power consumption, area overhead, and complexity, especially with a large number of cascaded stages.
Innovation Solution
Implementing a VCO-based continuous-time pipelined ADC with a CT residue generation front end and a CT VCO ADC back end, which includes digital non-linearity correction and a unique digital signal reconstruction filter to alleviate noise and distortion, reducing the number of stages and complexity while maintaining high resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a VCO ADC is used, then power consumption and area are reduced, but bandwidth and performance are limited due to inherent non-linearity and noise shaping
Solution Approach 1:
The ADC is divided into multiple stages: a first VCO ADC stage that processes the input signal and generates a first digital output, followed by a second VCO ADC stage that processes a scaled version of the input signal and generates a second digital output. This segmentation allows each stage to operate within its optimal performance range while collectively achieving higher overall bandwidth and resolution.
Solution Approach 2:
The patent implements a nested structure where a second VCO ADC is embedded within the overall ADC architecture, processing a scaled version of the input signal. The outputs from both VCO ADC stages are combined through digital signal processing, creating a nested configuration that achieves high performance with reduced power consumption compared to traditional single-stage designs.
2Measurement precision
If traditional CT pipelined ADC with many cascaded stages is used, then resolution is improved, but power consumption, area overhead, and complexity increase
Solution Approach 1:
The patent changes the operating parameters of the VCO ADC stages, specifically using different scaling factors for the input signals to each stage. The first VCO ADC processes the full-scale input signal, while the second VCO ADC processes a scaled version (e.g., half-scale). This parameter change allows the system to achieve high resolution with fewer stages by exploiting the non-linearity characteristics at different signal levels.
Solution Approach 2:
The patent replaces the traditional mechanical/analog signal path with digital signal processing. Instead of using multiple analog amplification and filtering stages, the invention uses digital scaling and combination of outputs from VCO ADC stages. This substitution of digital processing for analog circuitry reduces complexity, power consumption, and area while maintaining high resolution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the bandwidth and resolution of the VCO ADC, reduces power consumption and silicon area, and simplifies digital signal processing, achieving performance comparable to traditional CT pipelined ADCs with fewer stages and less complex circuitry.
Implementation Method 1
a voltage-controlled-oscillator (VCO) ADC back end to sample phase of the amplified residue signal
Data Source
AI summary
VCO ADCs consume relatively little power and require less area than other ADC architectures. However, when a VCO ADC is implemented by itself, the VCO ADC can have limited bandwidth and performance. To address these issues, the VCO ADC is implemented as a back end stage in a VCO-based continuous-time (CT) pipelined ADC, where the VCO-based CT pipelined ADC has a CT residue generation front end. Optionally, the VCO ADC back end has phase interpolation to improve its bandwidth. The pipelined architecture dramatically improves the performance of the VCO ADC back end, and the overall VCO-based CT pipelined ADC is simpler than a traditional continuous-time pipelined ADC.