CTDSM Input Path Delay Matching for Residue Reduction
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Solution Overview
Problem
In pipelined continuous-time Analog-to-Digital Converters (ADCs), particularly in CTDSM-based ADCs, the input signal residue generation is erroneous due to unmatched magnitude and phase in the coarse path, leading to overloading in subsequent stages, especially at high frequencies, which existing solutions address with power-intensive prediction filters.
Innovation Solution
The implementation of an input delay circuit as a passive filter network, including low-pass and all-pass filters, or a digitally controlled delay, in the continuous-time input path to match the magnitude and phase, with digital delay lines used to calibrate and minimize residue, reducing the need for power-intensive circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a prediction filter is inserted in the coarse ADC path to compensate for delay, then phase matching is improved, but circuit area and power consumption increase
Solution Approach 1:
The patent replaces the active analog prediction filter (mechanical/electrical system with power consumption) with a digital delay line and digital signal processing. The digital system uses sampled data and computational delay to achieve phase matching without the continuous power consumption of active analog filters, thereby substituting a power-intensive mechanical/electrical system with a digital computational approach.
Solution Approach 2:
The patent changes the approach from continuous analog filtering to discrete digital delay by adjusting the delay parameter in the digital domain. Instead of using an active filter with continuous power consumption, the system uses a digitally controlled delay line that can be tuned to match phase characteristics, achieving the same functional goal with different operational parameters and reduced power usage.
2Manufacturing precision
If a prediction filter is inserted in the coarse ADC path to compensate for delay, then phase matching is improved, but circuit area increases
Solution Approach 1:
The patent replaces the active analog prediction filter (mechanical/electrical system occupying circuit area) with a digital delay line and digital signal processing. The digital implementation uses logic elements and memory structures that can be more efficiently packed in standard cell libraries, reducing the overall circuit area compared to discrete active filter components and their associated biasing circuits.
Solution Approach 2:
The digital delay line and processing logic can serve multiple functions: phase matching, delay compensation, and signal routing. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby reducing overall circuit area compared to specialized analog filter implementations that require dedicated components for each function.
3Device complexity
If the input signal path is not matched in magnitude and phase, then circuit complexity is reduced, but residue generation error increases
Solution Approach 1:
The patent introduces a digital delay line as an intermediary element between the coarse ADC output and the residue generation stage. This intermediary component compensates for the phase and delay mismatch without requiring complex analog circuit modifications. The digital delay line acts as a mediator that aligns the signals in the digital domain, maintaining simplicity in the analog front-end while achieving precise residue generation.
4Device complexity
If the input signal path is not matched in magnitude and phase, then circuit design is simplified, but overloading in subsequent stages increases
Solution Approach 1:
The digital delay line serves as an intermediary that prevents harmful overloading effects by aligning phase and delay before signals are combined in the residue generation stage. This intermediary component eliminates the harmful interaction between mismatched signals that would otherwise cause overloading, while keeping the overall circuit design simple and avoiding complex analog matching networks.
Data Source
AI summary
System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.