CT Delta-Sigma Integrator Gain Compensation for Low-Power Linearity
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Solution Overview
Problem
Continuous-time delta-sigma modulators (CTDSMs) face limitations in linearity and power consumption due to the linearity of the first integrator in its loop filter, especially at high sampling frequencies, which affects their ability to achieve ultra-high linearity and suppress quantization noise effectively.
Innovation Solution
Implementing a single-stage inverter-based amplifier with gain compensation, utilizing a gain compensation circuit to enhance the signal-to-quantization-noise ratio (SQNR) while reducing power consumption by moving the gain compensation stage further in the signal chain, and employing a cascaded-integrated-feedforward (CIFF) architecture with resonators and capacitors to minimize noise and distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a single-stage inverter-based amplifier is used in the first integrator, then power consumption is reduced, but the amplifier gain is limited which affects linearity and quantization noise suppression
Solution Approach 1:
The amplifier function is divided into two separate stages: a single-stage inverter-based amplifier for power efficiency, and a dedicated gain compensation circuit for linearity restoration. This segmentation allows each stage to be optimized for its specific function, resolving the contradiction between low power consumption and high linearity.
Solution Approach 2:
A gain compensation circuit is introduced as an intermediary element between the limited-gain amplifier and the rest of the modulator. This intermediary compensates for the gain limitation, enabling the system to achieve ultra-high linearity without requiring the main amplifier to have high gain, thus maintaining low power consumption.
2Reliability
If gain compensation is implemented early in the signal chain, then linearity is improved, but power consumption increases
Solution Approach 1:
The gain compensation is performed preliminarily on the feedback signal before it enters the first integrator, rather than requiring continuous high-gain amplification throughout the signal chain. This preliminary action establishes the necessary gain early, allowing subsequent stages to operate with lower power consumption while maintaining linearity.
3Measurement precision
If multi-stage amplifiers are used to achieve high gain, then quantization noise suppression is improved, but device complexity and power consumption increase
Solution Approach 1:
The amplification function is segmented into a simple single-stage inverter amplifier and a separate gain compensation circuit, avoiding the need for complex multi-stage amplifiers. This segmentation achieves the same quantization noise suppression performance with significantly reduced device complexity.
Solution Approach 2:
Instead of using a complex multi-stage amplifier design, the patent uses a simplified single-stage amplifier copy combined with a gain compensation mechanism. This copying approach replicates the essential amplification function while eliminating the complexity of multiple stages, achieving equivalent noise suppression performance.
Data Source
AI summary
A modulator circuit may include an integrator circuit and a gain compensation circuit. The integrator circuit may include a first amplifier including an input to receive a signal and an output to provide an inverted signal and a capacitor including a first terminal coupled to the input and a second terminal coupled to the output. The gain compensation circuit may include a second inverter amplifier including a gain input coupled to the output of the first amplifier and including a gain output; a first resistor including a first terminal coupled to the gain output and including a second terminal; and a second capacitor including a first terminal coupled to the second terminal of the first resistor and including a second terminal coupled to the gain input. The integrator circuit has a finite DC gain and the gain compensation circuit is configured to compensate for the finite DC gain.