CTE Graded Layer for Copper TSV Stress Reduction
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Solution Overview
Problem
The coefficient of thermal expansion (CTE) mismatches between copper TSV filler materials and semiconductor substrates lead to significant thermally induced stress, causing diffusion barrier metal layer failures such as peeling or cracking, which allows copper migration into the substrate, compromising the integrity of semiconductor ICs.
Innovation Solution
A CTE graded layer with a non-constant chemical composition profile is introduced between the substrate and the copper TSV filler, increasing CTE from the substrate side to the copper side, reducing the CTE mismatch and stress through deposition processes like ALD or PECVD, using materials such as silicon oxide transitioning to polysilicon or silicon carbide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper is used as TSV filler material, then electrical conductivity is improved, but thermal expansion mismatch causes stress and barrier layer failure
Solution Approach 1:
A CTE graded layer is introduced as an intermediary between the copper TSV filler and the silicon substrate. This layer has a chemical composition that varies through its thickness, creating a gradient in coefficient of thermal expansion. The CTE of the graded layer transitions from matching the substrate at the interface to matching the copper filler at the other interface, thereby mediating the thermal expansion mismatch and reducing interfacial stress.
Solution Approach 2:
The chemical composition parameter of the dielectric layer is changed through its thickness to create a CTE gradient. By controlling the composition profile (e.g., varying silicon oxide content), the CTE parameter varies continuously from the substrate side to the copper side, allowing the layer to accommodate differential thermal expansion without generating excessive stress.
2Reliability
If diffusion barrier metal layer is added to prevent copper migration, then reliability is improved, but CTE mismatch causes barrier layer peeling or cracking
Solution Approach 1:
The CTE graded layer serves as a stress-mediating intermediary between the barrier metal layer and the silicon substrate. By providing a gradual transition in CTE, it reduces the interfacial stress that would otherwise cause the barrier layer to peel or crack, thereby preserving barrier layer integrity while maintaining its copper migration prevention function.
Solution Approach 2:
The CTE graded layer acts as a cushioning layer deposited beforehand to absorb and distribute thermal stress. This pre-positioned stress-absorbing layer prevents stress concentration at the barrier metal-substrate interface, protecting the barrier layer from thermal shock during subsequent processing and operation.
3Object-affected harmful factors
If TSV diameter is reduced and spacing is increased to reduce stress, then thermal stress is reduced, but device density decreases
Solution Approach 1:
Instead of changing the geometric parameters (TSV diameter and spacing), the invention changes the material parameter (CTE gradient in the dielectric liner) to reduce thermal stress. This allows maintaining small TSV dimensions and high density while the graded CTE profile absorbs thermal expansion differences, preventing stress-related failures.
4Object-affected harmful factors
If tungsten is used instead of copper as TSV filler, then CTE mismatch is reduced, but electrical conductivity decreases
Solution Approach 1:
The CTE graded layer enables the use of copper by mediating its thermal expansion mismatch with the substrate. This intermediary structure allows copper's superior electrical conductivity to be utilized while the graded layer absorbs the CTE difference, making copper a viable TSV filler material despite its high CTE.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CTE graded layer significantly reduces interfacial stress, minimizing diffusion barrier metal layer failures and copper migration, thereby enhancing the reliability and performance of semiconductor ICs by maintaining the integrity of the TSVs.
Implementation Method 1
using materials such as silicon oxide transitioning to polysilicon or silicon carbide
Implementation Method 2
using materials such as silicon oxide transitioning to polysilicon or silicon carbide
Implementation Method 3
The coefficient of thermal expansion (CTE) is defined as the fractional increase in the length per unit rise in temperature. Copper, as well as some other TSV filler materials, have a significantly higher CTE as compared to conventional semiconductor substrates, such as silicon
Data Source
AI summary
A semiconductor die includes a substrate including a topside including circuit elements configured to provide a circuit function. The die includes at least one multi-layer structure including a first material having a first CTE, a second material including a metal having a second CTE, wherein the second CTE is higher than the first CTE. A coefficient of thermal expansion (CTE) graded layer includes at least a dielectric portion that is between the first material and the second material having a first side facing the first material and a second side facing the second material. The CTE graded layer includes a non-constant composition profile across its thickness that provides a graded CTE which increases in CTE from the first side to the second side. The multi-layer structure can be a through-substrate-vias (TSV) that extends through the thickness of the substrate.