CTE-Matched Interposer with Metal-Filled Double Vias
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Solution Overview
Problem
In modern electronic devices, the mismatch in thermal expansion coefficients between different materials leads to cracking and reliability issues during manufacturing and use, particularly in densely packed components with metal and silicon vias, where conventional solutions like underfilling and complex CTE matching are inadequate.
Innovation Solution
A rigid interposer with tailored coefficient of thermal expansion (CTE) is designed, featuring double vias with a narrow and wide portion, where the narrow part is filled with metal and the wide part has a liner layer, allowing for CTE matching between silicon dies and plastic or ceramic circuit boards, reducing thermal stress and eliminating the need for complex handling and underfilling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal vias are used in densely packed substrates, then electrical connectivity is improved, but thermal expansion mismatch causes cracking and reliability issues
Solution Approach 1:
The patent uses a composite interposer structure combining silicon substrate with metal-filled vias and copper pillars, where each material is strategically placed to fulfill specific functions while managing thermal expansion differences through the composite architecture
Solution Approach 2:
The interposer acts as an intermediary component between the silicon die and PCB, absorbing and distributing thermal stress through its specially designed structure with metal-filled vias and copper pillars, preventing direct transmission of thermal expansion forces to the fragile silicon die
2Productivity
If via density is increased for high-density interconnects, then signal routing capability is improved, but thermal stress concentration increases causing substrate cracking
Solution Approach 1:
The patent applies local quality by having different via structures in different regions: metal-filled vias in certain areas and copper pillars in others, allowing localized optimization of thermal and electrical properties while maintaining high overall via density
Solution Approach 2:
The interposer is segmented into different functional regions with various via types and copper pillar arrangements, distributing thermal stress across multiple zones rather than concentrating it uniformly, enabling higher via density without proportional increase in cracking risk
3Length of moving object
If substrate thickness is reduced to 100 μm for thin chip mounting, then device miniaturization is improved, but substrate becomes too fragile to handle without carriers
Solution Approach 1:
The patent changes the thickness parameter of the interposer to 150-200 μm, which is thin enough for miniaturization but thick enough to provide sufficient mechanical strength for carrier-free handling, representing an optimized parameter value that balances both requirements
4Reliability
If conventional underfill is used to reduce thermal stress, then thermal expansion mismatch is alleviated, but complex handling and hermetic sealing requirements increase process complexity
Solution Approach 1:
The patent extracts and eliminates the underfill step from the conventional packaging process by incorporating thermal stress management directly into the interposer structure through metal-filled vias and copper pillars, simplifying the overall packaging architecture while maintaining thermal stress relief functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces thermal stress fractures, enhances heat transfer, and simplifies handling by matching CTE across wide ranges, making it cost-efficient and suitable for high-density interconnects without compromising reliability.
Implementation Method 1
different thermal expansion effects may lead to substrates being subject to cracking and breaking during manufacturing
Implementation Method 2
enhances heat transfer
Data Source
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AI summary
The inventive merit of the present interposer is that it is possible to taylor the coefficient of thermal expansion CTE of the interposer to match components to be attached thereto within very wide ranges. The invention relates to a emiconductor interposer, comprising a substrate (10) of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer- through via (18, 28, 27) comprising metal (27). At least one recess (20)is provided in the first side of the substrate (10) and in the semiconductor material of the substrate, the recess being filled with metal and connected with the wafer-through via providing a routing structure (20). The exposed surfaces of the metal filled via and the metal filled recess (18, 27) are essentially flush with the substrate surface on the first side of the substrate. The wafer-through via (18, 28, 27) comprises a narrow part (18) and a wider part (27), and there are provided contact elements on said routing structure (20) having an aspect ratio, height:diameter, < 1:1, preferably 1:1 to 2:1.