Digitally-Calibrated CTIA Pixel Circuit Area Reduction
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Solution Overview
Problem
Existing CTIA pixel circuits consume a large physical area due to the number and size of transistors required for zero-biased high conversion gain, hindering image sensor miniaturization and pixel density.
Innovation Solution
A CTIA pixel circuit design featuring a photoelectric conversion device, a series connection of two amplifier transistors, a feedback capacitor, and reset switches, including a cascode transistor layout to reduce area consumption and enhance gain, while maintaining zero-bias and high conversion gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a CTIA pixel circuit uses a relatively large number of transistors with large size to reduce offset voltage and achieve zero-biased high conversion gain, then the conversion gain and zero-bias performance are improved, but the physical area consumed by the pixel circuit increases
Solution Approach 1:
The pixel circuit is divided into functional blocks: photoelectric conversion device, CTIA circuit with amplifier and feedback capacitor, and digitally-controlled offset cancellation circuit. This segmentation allows each block to be optimized independently, reducing the overall area while maintaining high conversion gain performance.
Solution Approach 2:
The invention uses digitally-controlled transistors to dynamically adjust and cancel offset voltages, replacing the need for large fixed-size transistors. By changing the control parameters (gate voltages) of the transistors, the circuit achieves zero-bias operation with high conversion gain while using smaller transistor sizes, thus reducing the pixel circuit area.
2Reliability
If the number and size of transistors in the CTIA pixel circuit are increased to reduce offset voltage, then the zero-bias performance is improved, but the device complexity increases
Solution Approach 1:
The invention implements a feedback mechanism where the digitally-controlled transistors continuously monitor and cancel offset voltages in the CTIA circuit. This feedback approach maintains reliable zero-bias performance without requiring an excessive number of large transistors, as the offset cancellation is achieved through active control rather than passive oversizing of components.
Solution Approach 2:
The offset cancellation circuit serves itself by using the same transistor technology and operating within the same pixel circuit environment. The digitally-controlled transistors automatically adjust their parameters to compensate for offsets, eliminating the need for external calibration or additional complex circuitry, thus improving reliability without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a compact pixel circuit architecture with improved gain and reduced noise, enabling more efficient image sensing with increased pixel density and reduced physical area usage.
Implementation Method 1
charge is collected in a photoelectric conversion device of the pixel circuit as a result of the impingement of light
Data Source
AI summary
A pixel circuit includes a photoelectric conversion device; an amplifier including a first amplifier transistor and a second amplifier transistor connected in series between a first voltage and a second voltage, wherein a gate terminal of the first amplifier transistor is connected to the photoelectric conversion device; a feedback capacitor connected between a first current terminal of the first amplifier transistor and the photoelectric conversion device; a first reset switch connected between the gate terminal of the first amplifier transistor and an anode voltage; and a second reset switch connected between a first current terminal of the second amplifier transistor and a gate terminal of the second amplifier transistor.