CTIA Pixel Shared Reset Network Leakage Reduction
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Solution Overview
Problem
Existing CTIA pixel circuits face issues with leakage current, which leads to low conversion gain and integral non-linearity degradation, making it difficult to achieve high conversion gain and minimize area in image sensors.
Innovation Solution
A CTIA pixel circuit design incorporating a three-transistor reset switch network and a shared reset switch network with a common reference voltage is implemented to minimize leakage current and reduce pixel area, allowing for higher conversion gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional reset switch is used in CTIA pixel circuit, then the circuit structure is simple, but leakage current occurs causing low conversion gain and integral non-linearity degradation
Solution Approach 1:
The reset switch is divided into three separate transistors (first reset transistor, second reset transistor, and third reset transistor) arranged in a specific configuration. This segmentation allows each transistor to control a specific portion of the reset function, enabling better control over leakage current paths while maintaining the overall reset functionality.
Solution Approach 2:
A body terminal connection is introduced as an intermediary element between the reset transistors and the reference voltage. This body terminal connection acts as a mediator that stabilizes the voltage at the body terminal of the reset transistors, preventing unwanted leakage currents while maintaining the reset switch's operational integrity.
2Area of stationary object
If pixel area is reduced to minimize area, then more pixels can be packed, but achieving high conversion gain becomes more difficult
Solution Approach 1:
The patent changes the electrical parameters of the reset switch network by introducing a body terminal connection to a common reference voltage. This parameter change allows the reset network to operate with lower leakage current, enabling high conversion gain to be maintained even in reduced-area pixels where conventional designs would fail.
3Reliability
If conversion gain is increased to improve signal quality, then leakage current effects become more pronounced, but area must be minimized
Solution Approach 1:
The patent converts the potentially harmful body terminal voltage variations into a beneficial control mechanism. By intentionally connecting the body terminal to a common reference voltage, the design transforms what would be a source of leakage current into a controlled voltage reference that stabilizes the reset network and reduces overall leakage effects, enabling high conversion gain operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes leakage current and increases conversion gain, achieving up to 60 μV/e− while reducing pixel area, thus addressing the challenges of low gain and area minimization in CTIA pixel circuits.
Implementation Method 1
charge is collected in a photoelectric conversion device of the pixel circuit as a result of the impingement of light
Implementation Method 2
a capacitor disposed between the first input terminal and the output terminal
Data Source
AI summary
An image sensor and pixel circuit therefor includes a plurality of pixels arranged in an array, a first pixel of the plurality of pixels including: a first photoelectric conversion device; a first amplifier including a first input terminal connected to the first photoelectric conversion device, and a first output terminal; a first capacitor disposed between the first input terminal and the first output terminal; and a first reset switch network disposed between the first input terminal and the first output terminal in parallel with the first capacitor, the first reset switch network including a first reset transistor with a first body terminal connected to a common reference voltage, a second reset transistor, and a third reset transistor.