CTLE Bias Current Switching for Stable Multi-Rate Data Links
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Solution Overview
Problem
Continuous time linear equalizers (CTLEs) face instability in their direct current (DC) operating points due to variations in data rates, leading to the inability to process input signals with slightly large amplitudes and output distorted signals as data rates increase, particularly in high-speed serial computer expansion bus standards like PCIe.
Innovation Solution
A CTLE circuit with adjustable bias current and input device size based on data rate, ensuring a substantially stable operating point across various data rates by selecting a subset of differential transistor groups to be driven by the bias current, maintaining a consistent safety margin between normal and clipping levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the data rate is increased to achieve higher communication speed, then the communication productivity is improved, but the DC operating point of the CTLE becomes unstable causing signal distortion
Solution Approach 1:
The patent implements dynamic adjustment of the bias current based on the detected data rate. The CTLE circuit includes a bias current generator that provides different bias current levels corresponding to different data rates (e.g., 4 Gbps, 8 Gbps, 16 Gbps). This dynamic adaptation allows the DC operating point to be optimized for each data rate, maintaining stability and preventing signal distortion while enabling high-speed communication.
Solution Approach 2:
The patent changes the bias current parameter according to the data rate to maintain stable DC operating conditions. By adjusting this key electrical parameter, the circuit adapts to different communication speeds while preserving signal integrity. The bias current is modified in conjunction with input device size selection to ensure the operating point remains stable across varying data rates.
2Productivity
If the bias current and input device size are increased to handle higher data rates, then the signal processing capability is improved, but the DC operating point shifts causing distortion
Solution Approach 1:
The patent employs dynamic configuration where both the bias current and input device size are adjusted together based on the data rate. This coordinated dynamic adjustment ensures that the increased signal processing capability does not destabilize the DC operating point. The system selects appropriate input devices and bias current levels from multiple available options to match the operating conditions.
Solution Approach 2:
The patent modifies multiple parameters simultaneously - the bias current and the input device size - to maintain proper DC operating conditions across different data rates. This multi-parameter adjustment approach allows the circuit to handle higher data rates with improved signal processing capability while preventing operating point shifts that would cause distortion.
3Device complexity
If a fixed CTLE configuration is used to simplify the circuit design, then the device complexity is reduced, but the performance consistency across different data rates deteriorates
Solution Approach 1:
The patent divides the CTLE circuit into multiple configurable segments, including multiple input devices with different sizes and multiple bias current levels. Each segment is optimized for specific data rate ranges. The circuit includes selection mechanisms that activate appropriate segments based on the detected data rate, providing performance consistency without requiring a completely different circuit design for each speed.
Solution Approach 2:
The patent creates a universal CTLE circuit that can operate across multiple data rates by incorporating multiple input devices and bias current options. This multi-functional design allows a single circuit to adapt to different communication speeds (4 Gbps, 8 Gbps, 16 Gbps, and beyond) while maintaining consistent performance characteristics, eliminating the need for separate dedicated circuits for each data rate.
Data Source
AI summary
An electronic device (e.g., a CTLE circuit of a receiver of a data link) includes a current source and two differential transistor groups. The current source is configured to generate a bias current according to a data rate of data carried by a pair of differential input signals. A subset of the two differential transistor groups is configured to be driven by the bias current to generate a pair of differential output signals from the pair of differential input signals. The two differential transistor groups include a first plurality of transistors receiving a first input signal and a second plurality of transistors receiving a second input signal. The first and second input signals form the pair of differential input signals. In some implementations, each transistor is coupled to a biasing circuit including a DC path coupled to an adjustable biasing voltage level for selecting and deselecting the respective transistor.