CTLE Filter Coefficient Optimization via DFE Training

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Solution Overview

Problem

Conventional serializer/deserializer (SerDes) systems face challenges in efficiently determining optimal coefficients for continuous time linear equalization (CTLE) filters, particularly in high-speed data transmission, where inter symbol interference needs to be effectively canceled without requiring extensive calculations or additional hardware.

Innovation Solution

A method using a decision feedback equalization (DFE) training block to iteratively determine voltage values for resistor and capacitor coefficients, identifying voltage differences, and generating optimal coefficients for a CTLE filter, which can be stored and provided to the front-end receiver without calculating eye height and width for all resistor and capacitor values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional methods are used to determine optimal CTLE coefficients, then accurate equalization can be achieved, but extensive calculations and additional hardware are required

Engineering Contradiction:
Improveequalization accuracyVSAvoidhardware complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The DFE training block leverages its existing decision feedback equalization functionality to simultaneously train both DFE and CTLE coefficients. The same training sequence and decision logic are reused, allowing the block to serve dual purposes without requiring separate dedicated hardware for CTLE coefficient determination.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The DFE training block is designed to perform multiple functions: it trains DFE coefficients, determines optimal CTLE coefficients, and provides training sequences. This multi-functional approach eliminates the need for separate specialized hardware blocks for each function, reducing overall system complexity while maintaining accuracy.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If conventional methods are used to determine optimal CTLE coefficients, then accurate equalization can be achieved, but extensive calculations increase processing time

Engineering Contradiction:
Improveequalization accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The system performs preliminary training by using the DFE training block to establish initial coefficient values before final CTLE optimization. This preliminary action provides a good starting point that reduces the search space and iteration requirements for achieving optimal coefficients, thereby reducing overall processing time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The decision feedback mechanism continuously monitors signal quality and uses this feedback to iteratively refine coefficient values. This feedback-driven approach converges to optimal coefficients more efficiently than exhaustive search methods, reducing processing time while maintaining accuracy.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If all resistor and capacitor values are evaluated to calculate eye height and width, then optimal coefficients can be found, but the process becomes computationally intensive

Engineering Contradiction:
Improvecoefficient optimizationVSAvoidtraining efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

Instead of evaluating all possible resistor and capacitor combinations, the system performs partial evaluation by focusing on a reduced set of candidate values guided by preliminary DFE training results. This partial action approach finds sufficiently optimal coefficients without the computational burden of exhaustive search across all possibilities.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11277285B1Continuous time linear equalization system and method
Publication Date: 2022.03.15 CADENCE DESIGN SYST INC
  • US11277285B1 patent drawing
  • US11277285B1 patent drawing
  • US11277285B1 patent drawing

AI summary

The present disclosure relates to an apparatus and method for continuous time linear equalization. Embodiments include determining, using a decision feedback equalization (“DFE”) training block, a voltage value for one or more resistor values. Embodiments may further include determining, using the DFE training block, a voltage value for one or more capacitor values and identifying a voltage difference between the voltage value for one or more resistor values and the voltage value for one or more capacitor values. Embodiments may further include iteratively performing the determining of the voltage value and identifying of the voltage difference for each of the plurality of capacitor values until the voltage difference is at one or more minimum values to generate one or more optimal resistor and capacitor coefficients for a continuous time linear equalization filter.