CTLE Feedback Circuit for Tunable DC Gain and Mid-Band Peaking

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Solution Overview

Problem

High-speed serial links face challenges in maintaining high performance due to increased power consumption and silicon area as data transmission speeds rise, and existing equalization methods are inadequate for efficient signal recovery in high-speed wireless data communication systems.

Innovation Solution

A continuous time linear equalization (CTLE) feedback circuit with tunable DC gain and mid-band correction is introduced, incorporating a transimpedance amplifier (TIA) and a feedback circuit with tunable resistors and capacitors to enhance frequency response and reduce feedback factor at high frequencies, allowing for adjustable gain and peaking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If interface speed increases to transmit more data, then data transmission capacity is improved, but power consumption and silicon area of the communication receiver increase

Engineering Contradiction:
Improvedata transmission capacityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic equalization by making the equalizer gain and bandwidth可调 (adjustable) through feedback control. The equalization parameters are dynamically adjusted based on the received signal characteristics to optimize performance at different data rates without requiring fixed high-power design for maximum speed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent introduces a feedback circuit that monitors the output of the continuous-time linear equalizer and adjusts the equalization parameters accordingly. This feedback mechanism enables automatic optimization of the equalizer performance, reducing the need for over-provisioning power and area to handle all possible data rates.

Inventive Principle:
Principle #23Feedback

2Productivity

If interface speed increases to transmit more data, then data transmission capacity is improved, but silicon area of the communication receiver increases

Engineering Contradiction:
Improvedata transmission capacityVSAvoidsilicon area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent designs a universal continuous-time linear equalizer that can operate across multiple data rates by adjusting its equalization parameters. This single multi-functional equalizer structure replaces what would otherwise require multiple specialized equalizers for different speed modes, significantly reducing the required silicon area.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If feedback factor is reduced at high frequencies, then maximum peaking is enhanced, but frequency response control becomes more complex

Engineering Contradiction:
Improvemaximum peakingVSAvoidfrequency response control
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the feedback factor as a function of frequency, specifically reducing it at high frequencies to enhance peaking. This is achieved by using frequency-dependent feedback networks that automatically adjust the feedback amount based on the input signal frequency, optimizing the frequency response without manual intervention.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP4236067A1Continuous time linear equalization (CTLE) feedback for tunable DC gain and mid-band correction
Publication Date: 2023.08.30 SAMSUNG DISPLAY CO LTD
  • EP4236067A1 patent drawingFigure 1
  • EP4236067A1 patent drawingFigure 2
  • EP4236067A1 patent drawingFigure 3A

AI summary

An analog front end (AFE) circuit including: a continuous time linear equalizer (CTLE) circuit; a transimpedance amplifier (TIA) connected to the CTLE circuit; and a feedback circuit including: a first transistor connected between a first output of the feedback circuit and a first node connected to a first current source; a second transistor connected between a second output of the feedback circuit and a second node connected to a second current source; and a first tunable resistor coupled between the first node and the second node, wherein: a first input of the feedback circuit is connected to a first output of the TIA; a second input of the feedback circuit is connected to a second output of the TIA; the second output of the feedback circuit is connected to a first input of the TIA; and the first output of the feedback circuit is connected to a second input of the TIA.