CTLE Shared Current Path for High-Bandwidth Equalization

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Solution Overview

Problem

Existing continuous time linear equalizers (CTLEs) face challenges in maintaining high operating frequency bandwidth due to increased internal capacitance, which limits their ability to effectively equalize data signals with high-frequency components.

Innovation Solution

A CTLE device with a shared path between internal loopback and calibration current paths, allowing for test mode operations using the loopback path and normal mode operations using the calibration path, thereby reducing internal parasitic capacitance and enhancing frequency bandwidth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate current paths are provided for test mode and normal mode operations, then the CTLE can perform both functions, but the internal capacitance increases and operating frequency bandwidth is reduced

Engineering Contradiction:

Improvemode operation capabilityVSAvoidoperating frequency bandwidth

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent merges the test current path and calibration current path into a single shared current path. The current path includes transistors that can be selectively activated based on operation mode, allowing both test and calibration functions to use the same physical circuitry rather than requiring separate dedicated paths for each function.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared current path is designed to serve multiple functions: it can operate as a test current path when test transistors are activated, and as a calibration current path when calibration transistors are activated. This multi-functional design eliminates the need for separate dedicated paths while maintaining both operational capabilities.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If multiple dedicated current paths are implemented for different functions, then functional completeness is achieved, but device complexity and internal capacitance increase

Engineering Contradiction:

Improvefunctional completenessVSAvoidcircuit path configuration

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple dedicated current paths into a single shared current path that accommodates both test mode and normal mode operations. By sharing the same physical path with selectively activated transistors, the circuit complexity is reduced while maintaining the ability to perform both test and calibration functions.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared current path is designed with universal functionality to handle both test and calibration operations. The path includes multiple transistor branches that can be selectively enabled based on the operational mode, allowing one physical path to replace what would traditionally require multiple separate paths.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12489482B2Continuous time linear equalizer and device including the same

Publication Date: 2025.12.02 SAMSUNG ELECTRONICS CO LTD

AI summary

A device includes a receiver analog front-end circuit including a path shared by an internal loopback current path and a calibration current path, wherein the receiver analog front-end circuit is configured to perform an internal test using the internal loopback current path while in a test mode, and equalize a first data signal while in a normal mode, the equalizing the first data signal including removing an offset from the first data signal using the calibration current path.