Cu-Cu Bonded Semiconductor Guard Ring Layout Against Voids and Moisture
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Solution Overview
Problem
The reliability of semiconductor devices with Cu—Cu junctions is compromised by dishing, void formation, and moisture infiltration, leading to reduced junction strength and potential corrosion, especially during dicing and power source pad opening.
Innovation Solution
A semiconductor device design incorporating guard ring units with multiple guard rings and Cu dummies on semiconductor substrates, along with slits and asymmetric formations, to enhance junction strength and prevent moisture ingress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a guard ring is formed on a Cu-Cu junction surface to improve connection strength, then junction strength is improved, but dishing occurs and concavities and convexities are easily formed on the junction surface
Solution Approach 1:
The guard ring is divided into multiple segments (first guard ring, second guard ring, third guard ring) rather than forming a continuous ring. This segmentation prevents the guard ring structure from causing dishing and surface irregularities while still providing crack prevention functionality. The segmented design allows the Cu-Cu junction surface to maintain flatness during CMP processing while the distributed guard ring structures continue to prevent inner cracks and chipping.
Solution Approach 2:
The guard ring structures are strategically positioned at specific locations where crack prevention is most needed (around the circumference of the semiconductor device and around power source pad openings) rather than forming a complete continuous ring. This localized approach provides crack prevention functionality only where required, avoiding the dishing problem that would occur with a complete guard ring while maintaining junction surface flatness in other areas.
2Reliability
If a continuous guard ring is formed to prevent inner cracks and chipping, then reliability is improved, but voids are easily generated on the junction surface
Solution Approach 1:
The continuous guard ring is segmented into multiple discrete guard ring structures. This segmentation eliminates the void formation problem that occurs with continuous guard rings during CMP processing, while the distributed segmented structures continue to provide effective crack prevention and chipping protection throughout the junction surface.
3Volume of moving object
If the Cu-Cu junction surface is used for space saving, then device size is reduced, but moisture infiltration causes wiring corrosion and reliability degradation
Solution Approach 1:
The segmented guard ring structures are positioned at strategic locations including around the circumference of the semiconductor device and around power source pad openings, creating localized barrier structures that prevent moisture infiltration at these critical areas while maintaining the compact Cu-Cu junction design for space saving.
4Manufacturing precision
If guard ring units are formed inside scribe lines to prevent chipping, then manufacturing quality is improved, but device complexity increases
Solution Approach 1:
The guard ring structures are implemented as simple segmented metal patterns within the scribe lines rather than complex continuous rings or three-dimensional structures. This segmented approach provides effective chipping and cracking prevention while maintaining relatively simple device structure and manufacturing processes.
Data Source
AI summary
A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, and at least one guard structure including a first guard element, a second guard element, and a third guard element. The first semiconductor substrate and the second semiconductor substrate are bonded to one another at a bonding interface between a surface of the first semiconductor substrate and a surface of the second semiconductor substrate. The first guard element is in the first semiconductor substrate and spaced apart from the third guard element by a portion of the first semiconductor substrate. The second guard element is in the second semiconductor substrate and spaced apart from the third guard element by a portion of the second semiconductor substrate, and the third guard element includes portions in the first surface and the second surface to bond the first semiconductor substrate to the second semiconductor substrate.