Cu Interconnect Dummy Insertion Algorithm for Planarization
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Solution Overview
Problem
Current dummy fill algorithms for copper interconnects in integrated circuit manufacturing, such as rule-based and model-based methods, fail to accurately control the thickness of the interlayer dielectric and metal density, leading to dishing defects and increased resistance, which complicates the manufacturing process and affects yield and reliability.
Innovation Solution
An algorithm that divides the semiconductor chip into square windows, calculates and adjusts the metal density and line width of dummy patterns within these windows to ensure uniformity and minimize density gradients, using a combination of logic operations and iterative calculations to determine optimal dummy pattern insertion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If rule-based dummy fill is used to improve overall metal density uniformity, then the simplicity and implementation ease are improved, but the control precision of interlayer dielectric thickness and metal density is worsened
Solution Approach 1:
The patent changes the parameters of dummy pattern insertion by considering both metal density and line width together rather than just density. It introduces a target density calculation that incorporates line width effects, and uses iterative adjustment of dummy pattern parameters to achieve the desired planarization outcome while maintaining manufacturing precision.
Solution Approach 2:
The patent performs preliminary calculation of target metal density and line width requirements before actual dummy pattern insertion. It pre-divides the layout into windows and calculates the needed dummy characteristics in advance, allowing for more precise control of the final interlayer dielectric thickness and metal density distribution.
2Manufacturing precision
If model-based dummy fill is used to achieve better planarization effect, then the manufacturing precision is improved, but the device complexity and computational resources required are worsened
Solution Approach 1:
The patent applies local quality by dividing the overall layout into separate windows and treating each window independently with its own target density and line width calculations. This localized approach allows for precise planarization control in each region while keeping the overall algorithm manageable and avoiding the complexity of global model-based methods.
3Manufacturing precision
If dummy pattern is inserted to improve metal density uniformity, then the planarization effect is improved, but the line width control and resistance variation are worsened
Solution Approach 1:
The patent simultaneously optimizes two parameters - metal density and line width - rather than just density. It calculates target values for both parameters and adjusts dummy pattern insertion to achieve both goals, thereby maintaining line width control precision while improving planarization effect and reducing resistance variation.
Data Source
AI summary
The present invention disclosed an algorithm of Cu interconnect dummy inserting, including: divide the surface of semiconductor chip into several square windows with an area of A, each of which is non-overlap; perform a logic operation on each square window; and divide the window into two parts: ① the area to-be-inserted; ② the non-inserting area; determine the metal density of the dummy pattern that should be inserted to each square window and the line width; determine the dummy pattern that should be inserted to the windows according to the metal density, line width, the pre-set dummy pattern and the layouting rules. The beneficial effects of the present invention is: avoided the shortcomings of fill density maximization in the rule-based filling method by using reasonable metal density and line width. And with a combination of the influence of line width and density to the copper plating process and chemical mechanical polishing morphology in model-based filling method, it can achieve a better planarization effect.