Cu Pillar Interlayer Structure for Packaging Stress Relief
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Solution Overview
Problem
Existing semiconductor devices experience stress during packaging due to the use of Cu pillars on Cu conductive layers, which can lead to reliability issues, especially in flip-chip packaging.
Innovation Solution
A semiconductor device is designed with an intermediate layer having a linear expansion coefficient lower than both the Cu conductive layer and the Cu pillar, which reduces stress during packaging by mitigating thermal expansion mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Cu pillars are used on Cu conductive layers for electrical connection, then electrical conductivity is improved, but stress is generated during packaging due to thermal expansion mismatch
Solution Approach 1:
An intermediate layer is introduced between the Cu pillar and Cu conductive layer. This intermediate layer acts as a stress buffer that absorbs thermal expansion mismatch during packaging processes, preventing stress concentration while maintaining electrical conductivity through the Cu pillar connection.
Solution Approach 2:
The linear expansion coefficient of the intermediate layer is specifically selected to be lower than that of both the Cu conductive layer and Cu pillar. This parameter optimization creates a gradient structure that gradually transitions thermal expansion properties, reducing stress during temperature changes in packaging while preserving electrical performance.
2Stress or pressure
If an intermediate layer with lower linear expansion coefficient is introduced between Cu conductive layer and Cu pillar, then stress during packaging is reduced, but device structure becomes more complex
Solution Approach 1:
The intermediate layer serves as a mediating element that resolves the thermal expansion mismatch problem. By positioning this layer between the Cu conductive layer and Cu pillar, it absorbs stress during packaging while adding minimal structural complexity to the overall device architecture.
Solution Approach 2:
The patent employs a composite structure combining the intermediate layer with Cu conductive layer and Cu pillar. This composite approach integrates materials with different thermal expansion properties in a controlled manner, achieving stress reduction during packaging while maintaining a manageable and systematic device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of the intermediate layer effectively reduces stress in semiconductor devices during packaging, enhancing the reliability of flip-chip packaged semiconductor packages.
Implementation Method 1
an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar
Data Source
AI summary
A semiconductor device includes a semiconductor layer having a first surface, an insulating layer formed at the first surface of the semiconductor layer, a Cu conductive layer formed on the insulating layer, the Cu conductive layer made of a metal mainly containing Cu, a second insulating layer formed on the insulating layer, the second insulating layer covering the Cu conductive layer, a Cu pillar extending in a thickness direction in the second insulating layer, the Cu pillar made of a metal mainly containing Cu and electrically connected to the Cu conductive layer, and an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar.