Cu Pillar Intermediate Layer for Packaging Stress Relief

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Solution Overview

Problem

Existing semiconductor devices experience stress during packaging due to the use of Cu pillars, which can compromise the reliability of the semiconductor package.

Innovation Solution

Incorporating an intermediate layer with a linear expansion coefficient smaller than both the Cu conductive layer and Cu pillar helps to mitigate stress during packaging, particularly in flip-chip packaging configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Cu pillar is used for electrical connection, then electrical conductivity is improved, but stress is generated during packaging due to thermal expansion mismatch

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidpackaging stress
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

An intermediate layer is introduced between the Cu pillar and Cu conductive layer to act as a stress buffer. This intermediary layer has a linear expansion coefficient that is smaller than both the Cu pillar and Cu conductive layer, allowing it to accommodate thermal expansion differences and reduce stress during packaging processes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The linear expansion coefficient parameter is strategically selected for the intermediate layer to be smaller than both adjacent Cu components. This parameter change creates a gradient structure that progressively manages thermal stress, with the intermediate layer absorbing expansion differences between the Cu pillar and the Cu conductive layer during temperature variations in packaging.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If Cu pillar is used to reduce connection resistance, then electrical performance is improved, but stress concentration occurs at the interface

Engineering Contradiction:
Improveconnection performanceVSAvoidinterface strength
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The intermediate layer serves as a mediator between the Cu pillar and Cu conductive layer, providing a transition zone that reduces stress concentration at the interface. This layer prevents direct stress transmission between the two Cu components, thereby protecting the interface from stress-induced failures while maintaining electrical connectivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The structure forms a composite material system consisting of Cu pillar-intermediate layer-Cu conductive layer. This composite structure combines materials with different mechanical and thermal properties to achieve both electrical performance and stress management, where the intermediate layer provides mechanical compliance while the Cu components provide electrical conductivity.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces stress in semiconductor devices, enhancing the reliability of the semiconductor package by improving stress management in flip-chip packaging.

Implementation Method 1

an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20250316638A1Semiconductor chip and semiconductor device including a copper pillar and an intermediate layer
Publication Date: 2025.10.09 ROHM CO LTD
  • US20250316638A1 patent drawing
  • US20250316638A1 patent drawing
  • US20250316638A1 patent drawing

AI summary

A semiconductor device includes a semiconductor layer having a first surface, an insulating layer formed at the first surface of the semiconductor layer, a Cu conductive layer formed on the insulating layer, the Cu conductive layer made of a metal mainly containing Cu, a second insulating layer formed on the insulating layer, the second insulating layer covering the Cu conductive layer, a Cu pillar extending in a thickness direction in the second insulating layer, the Cu pillar made of a metal mainly containing Cu and electrically connected to the Cu conductive layer, and an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar.