Cu Post Height Difference Mitigates Leakage in Semiconductor Packaging
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Solution Overview
Problem
Current semiconductor packaging technologies face contamination issues due to copper (Cu) residues, which affect the electrical properties of devices with high density and small spacing, as Cu is malleable and leaves residues after planarization, leading to potential electrical property degradation.
Innovation Solution
A method involving a silicon substrate with a groove, an insulating layer, and a Cu post, where dry etching creates a first height difference between the substrate and the insulating layer, followed by a wet etch process to remove Cu residues and form a second height difference, ensuring the first height difference is greater than the second, and a passivation layer is applied to prevent conductive channels and contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Cu layer is used for high density and small spacing, then conductivity is improved, but Cu residues remain after planarization causing contamination
Solution Approach 1:
The patent segments the Cu layer into isolated Cu posts surrounded by insulating layers, preventing Cu residues from forming continuous conductive paths that would cause contamination. The insulating layer acts as a barrier that segments and isolates Cu structures.
Solution Approach 2:
The patent extracts and removes Cu residues through selective wet etching processes. The insulating layer is designed to be resistant to the etchant while Cu residues are selectively removed, effectively extracting the harmful component from the structure.
2Manufacturing precision
If planarization is performed on Cu layer, then surface flatness is improved, but Cu residues are left behind
Solution Approach 1:
The patent applies preliminary protective action by forming the insulating layer around Cu structures before planarization. This insulating layer protects Cu from oxidizing during planarization and prevents Cu residues from adhering to the planarization tool, while still allowing the Cu surface to be planarized.
Solution Approach 2:
The insulating layer acts as an intermediary between the Cu layer and the planarization process. It mediates the interaction by protecting Cu from direct exposure to planarization tools while allowing the Cu surface to be flattened, and subsequently facilitates selective removal of Cu residues.
3Reliability
If Cu density is increased for better performance, then energy efficiency is improved, but risk of Cu contamination increases
Solution Approach 1:
The patent applies local quality by creating localized insulating barriers around each Cu post. This allows high Cu density in specific locations while maintaining local isolation that prevents contamination spread. Each Cu structure has its own protective insulating environment.
Solution Approach 2:
The patent converts the potential harm of Cu residues into a benefit by using the insulating layer to selectively remove Cu residues through wet etching. The same insulating layer that protects during planarization also enables selective Cu residue removal, turning the protection function into a contamination removal mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively removes Cu residues and prevents electrical property degradation by avoiding Cu connections across the insulating layer, ensuring a desirable insulation effect and maintaining the integrity of the semiconductor device's electrical properties.
Implementation Method 1
dry etching the Si substrate to configure a first height difference between the Si substrate and the insulating layer
Implementation Method 2
performing a wet etch process to remove Cu residues and a part of the Cu post
Implementation Method 3
an etchant solution used during the wet etch process includes an acid solution for chemical reacting with Cu
Implementation Method 4
forming a passivation layer to cover the Si substrate, the insulating layer, and the Cu post
Data Source
AI summary
The present disclosure provides a semiconductor structure and a method preparing it. After planarization of the Cu layer, a Si substrate is dry etched, so that a first height difference is configured in between the top surfaces of the the Si substrate and an insulating layer. By means of a wet etch process, Cu residues near an edge of a Cu post may be effectively removed. A second height difference is configured in between the top surfaces of the Cu post and the insulating layer. The first height difference is arranged to be greater than the second height difference. Channeling of Cu trace residues through the insulating layer are thereby avoided, effectively mitigating electrical leakage. Further, the Si substrate may be covered by a passivation layer, to prevent a conductive channel from being formed on the Si substrate, thereby further avoiding negative impact on the electrical properties of the device.