Semiconductor Cu Post Structure for Copper Residue Isolation
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Solution Overview
Problem
In semiconductor manufacturing, copper residues left after planarization processes in wafer-level packaging technology can adversely affect the electrical properties of devices with high density and small spacings, necessitating a method to completely remove these residues.
Innovation Solution
A method involving a silicon substrate patterning, forming an insulating layer and a copper post, followed by planarization, a wet etch process to remove copper residues and part of the post, and dry etching to create specific height differences between the copper post, insulating layer, and substrate, using an acid solution like H2O2, H3PO4, and H2SO4, and mechanical or chemical mechanical polishing techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper is used as conductive material in WLP technology, then electrical conductivity is improved, but copper residues remain after planarization which deteriorate electrical properties of high density devices
Solution Approach 1:
The patent applies preliminary action by performing wet etching before final planarization to pre-remove copper residues. The etching process uses acid solutions (H2O2, H3PO4, H2SO4) to chemically remove copper traces from the surface before the copper layer is fully planarized, preventing residue formation that would otherwise harm electrical properties of subsequent high density interconnect layers
Solution Approach 2:
The patent extracts harmful copper residues from the system by selectively removing copper material through wet etching. The acid-based etchant solution specifically targets and removes copper traces while leaving other materials intact, separating the harmful residues from the functional copper conductors
2Object-generated harmful factors
If wet etch process is used to remove copper residues, then copper residues are removed, but part of the copper post is also removed creating height difference
Solution Approach 1:
The patent applies local quality by creating intentional local height differences in the copper post structure. The wet etch process selectively removes copper from specific regions (creating recesses) while leaving other regions intact, resulting in copper posts with different heights in different locations. This local variation is designed to prevent copper residue formation while maintaining electrical functionality
Solution Approach 2:
The patent converts the harmful effect of copper removal into a beneficial outcome. By intentionally removing part of the copper post through wet etching, the process prevents copper residues from forming on the surface. The height difference created is not seen as a defect but as a feature that eliminates the harmful residue problem
3Manufacturing precision
If dry etching is used to create height difference between Si substrate and insulating layer, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent replaces mechanical polishing with chemical etching processes to achieve height differences. Instead of using mechanical forces to remove material and create the required height variations, the process uses chemical reactions (wet etching with acid solutions and dry etching with plasma) to selectively remove materials, achieving precise height control through chemical means
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively removes copper residues and prevents connections between copper materials inside and outside the insulating layer, thereby enhancing the electrical properties of the semiconductor device by creating controlled height differences.
Implementation Method 1
an etchant solution used during the wet etch process includes an acid solution facilitating a chemical reaction with Cu, and the acid solution includes one or a mixture of an H2O2 solution, an H3PO4 solution, and an H2SO4 solution
Implementation Method 2
dry etching the Si substrate to form a second height difference between the Si substrate and the insulating layer
Implementation Method 3
the planarization includes one or more of mechanical polishing method and chemical mechanical polishing method
Data Source
AI summary
The present disclosure provides a semiconductor structure and a method for preparing it. After planarization of the Cu layer, by means of wet etch process, Cu residues near an edge of a Cu post can be effectively removed, and a first height difference is configured to be between the Cu post and an insulating layer. Further, an Si substrate is then dry etched, so that a second height difference is configured to be between the Si substrate and the insulating layer, and the second height difference is arranged to be greater than the first height difference. In this way, a connection of Cu inside and outside the insulating layer may be further avoided, thereby effectively avoiding an influence on electrical properties of a device.