Cu-Ti Bonded Wiring Interface for Low-Resistance Semiconductor Stacking

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Solution Overview

Problem

The resistance of the bonding portion of the wiring at the interface between substrates in semiconductor devices increases after polishing, leading to reduced yield due to potential connection failures.

Innovation Solution

A semiconductor device with a first and second connection wiring layer, each comprising a trench with a barrier metal film containing Ti and a conductive film of polycrystalline Cu, where Ti and O are present on the bonding surface, allowing for bonding and heat treatment to replace copper oxide with titanium oxide, reducing connection resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If substrates are polished to flatten bonding surfaces, then bonding quality is improved, but resistance of bonding portion increases

Engineering Contradiction:
Improveflatness of bonding surfaceVSAvoidconnection resistance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a protective film on the bonding surface before polishing. This protective film prevents oxidation of the conductive layer during subsequent processing steps, thereby maintaining low resistance even after polishing. The protective film is formed in advance to counteract the harmful effect of polishing-induced oxidation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary substance (protective film made of silicon nitride or silicon oxide) between the conductive layer and the oxidizing environment. This intermediary layer prevents direct contact between oxygen and the conductive material, thus preventing resistance increase while allowing the bonding surface to be polished flat.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If polishing is performed on bonding surfaces, then substrate flatness is improved, but yield decreases due to connection failures

Engineering Contradiction:
Improveflatness of bonding surfaceVSAvoidyield
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The protective film is formed on the bonding surface before polishing to prevent oxidation. This preliminary protection ensures that subsequent polishing does not lead to connection failures, thereby maintaining high yield while achieving the required flatness for good bonding quality.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent converts the potentially harmful effect of polishing (which exposes conductive material to oxidation) into a beneficial process by having the protective film already in place. The polishing process becomes harmless because the protective film absorbs the oxidative exposure, preventing resistance increase and connection failures that would reduce yield.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration improves the yield by suppressing connection failures at the bonding interface by lowering the resistance between electrodes, enhancing the bonding quality and reliability of the semiconductor device.

Implementation Method 1

a first barrier metal film provided in the first trench and containing Ti, and a first conductive film provided in the first trench via the first barrier metal film and containing polycrystalline Cu

Methodology Applied
Scientific EffectOxidation barrier: Diffusion Barrier

Implementation Method 2

allowing for bonding and heat treatment to replace copper oxide with titanium oxide, reducing connection resistance

Methodology Applied
Scientific EffectPhase transformation: Phase Change

Data Source

PatentUS20240006359A1Semiconductor device and method of manufacturing semiconductor device
Publication Date: 2024.01.04 KIOXIA CORP
  • US20240006359A1 patent drawing
  • US20240006359A1 patent drawing
  • US20240006359A1 patent drawing

AI summary

In a semiconductor device according to an embodiment, a first connection wiring layer and a second connection wiring layer are bonded such that a first surface and a second surface face each other and a first electrode and a second electrode are in contact with each other, wherein the first electrode includes a first barrier metal film provided in a first trench and containing Ti, and a first conductive film provided in the first trench via the first barrier metal film and containing polycrystalline Cu, the second electrode includes a second barrier metal film provided in a second trench and containing Ti, and a second conductive film provided in the second trench via the second barrier metal film and containing polycrystalline Cu, and Ti and O are present on a bonding surface between the first electrode and the second electrode.