Cu Wiring Surface Void Reduction via CSL Boundary Control
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Solution Overview
Problem
Current semiconductor manufacturing techniques for Cu wiring fail to effectively control surface voids, leading to reduced reliability and increased manufacturing costs due to electro migration and stress migration, necessitating a method to universally maintain low surface void densities across various wiring generations.
Innovation Solution
A semiconductor device with Cu wiring is developed, featuring a composite layer of a barrier layer and a seed layer where the grain boundary characteristics, specifically a CSL boundary frequency of 60% or more, are optimized to reduce surface voids to 1/10 of the conventional level, achieved by controlling the grain boundary properties through specific material combinations and processing conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Cu wiring is used for high integration LSI, then wiring resistance and electro migration problems are improved, but surface voids form after CMP process leading to wiring disconnection
Solution Approach 1:
The invention changes the crystallographic parameters of the Cu wiring by controlling the grain boundary characteristics, specifically increasing the proportion of CSL boundaries with Σ value of 3 to 40% or more. This parameter change in the microstructure reduces surface void formation while maintaining the low resistance and electro migration resistance properties of Cu wiring
Solution Approach 2:
The invention uses a composite layer structure consisting of a barrier layer and a seed layer with specific grain boundary characteristics. The seed layer is designed with controlled CSL boundaries to create a composite material system that suppresses surface void formation during CMP processing while maintaining electrical performance
2Productivity
If wiring width is reduced for scaling, then integration density is improved, but surface voids lead to critical voids and wiring disconnection
Solution Approach 1:
The invention changes the microstructural parameters of the Cu wiring by controlling grain boundary characteristics, specifically increasing CSL boundaries with Σ value of 3 to 40% or more. This enables reliable miniaturization by suppressing surface void formation that would otherwise cause critical failures in scaled-down wiring structures
Solution Approach 2:
The invention performs preliminary control of grain boundary characteristics during the wiring formation process, establishing the desired CSL boundary proportion before CMP processing. This preliminary action prevents surface void formation from occurring in the first place, enabling reliable scaling to smaller wiring widths
3Ease of manufacture
If conventional Cu wiring formation process is used, then manufacturing simplicity is maintained, but surface voids decrease yield and increase manufacturing cost
Solution Approach 1:
The invention modifies the seed layer formation parameters to control grain boundary characteristics, specifically targeting CSL boundaries with Σ value of 3 to 40% or more. This parameter change is integrated into the existing Cu wiring formation process, maintaining ease of manufacture while significantly improving yield by reducing surface voids
Solution Approach 2:
The invention introduces feedback control by measuring and adjusting the grain boundary characteristics (CSL boundary proportion) during the seed layer formation process. This feedback mechanism ensures consistent suppression of surface voids while maintaining process simplicity and high manufacturing yield
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The optimized grain boundary characteristics significantly reduce surface voids, enhancing the reliability and yield of Cu wiring, even as wiring scales down, thereby addressing the challenges of electro migration and stress migration.
Implementation Method 1
a seed layer of such as pure Cu or Cu alloy to serve as a seed for electroplating Cu wiring formation
Implementation Method 2
excessive Cu (overlay portion) other than Cu in trenches for wiring formation is removed using CMP
Data Source
AI summary
A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.